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macOS-related weird errors #170

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ghost opened this issue Mar 12, 2017 · 10 comments
Closed

macOS-related weird errors #170

ghost opened this issue Mar 12, 2017 · 10 comments

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@ghost
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ghost commented Mar 12, 2017 •
edited by ghost

Hello,

I tried chipsec on my iMac from 2011 and 2015 (SIP was completely disabled then I tried again with "csrutil --without kext" with no success) and on both of these I got the following:

iMac Mid 2011:

[CHIPSEC] ***************************  SUMMARY  ***************************
[CHIPSEC] Time elapsed          0.743
[CHIPSEC] Modules total         17
[CHIPSEC] Modules failed to run 7:
ERROR: chipsec.modules.common.bios_smi
ERROR: chipsec.modules.common.ia32cfg
ERROR: chipsec.modules.common.smrr
ERROR: chipsec.modules.common.secureboot.variables
ERROR: chipsec.modules.common.uefi.access_uefispec
ERROR: chipsec.modules.common.uefi.s3bootscript
ERROR: chipsec.modules.smm_dma
[CHIPSEC] Modules passed        7:
[+] PASSED: chipsec.modules.common.bios_kbrd_buffer
[+] PASSED: chipsec.modules.common.bios_ts
[+] PASSED: chipsec.modules.common.smm
[+] PASSED: chipsec.modules.common.spi_fdopss
[+] PASSED: chipsec.modules.common.spi_lock
[+] PASSED: chipsec.modules.memconfig
[+] PASSED: chipsec.modules.remap
[CHIPSEC] Modules failed        2:
[-] FAILED: chipsec.modules.common.bios_wp
[-] FAILED: chipsec.modules.common.spi_desc
[CHIPSEC] Modules with warnings 1:
[!] WARNING: chipsec.modules.common.rtclock
[CHIPSEC] Modules skipped 0:
[CHIPSEC] Modules with Exceptions 7:
ERROR: chipsec.modules.common.bios_smi
ERROR: chipsec.modules.common.ia32cfg
ERROR: chipsec.modules.common.smrr
ERROR: chipsec.modules.common.secureboot.variables
ERROR: chipsec.modules.common.uefi.access_uefispec
ERROR: chipsec.modules.common.uefi.s3bootscript
ERROR: chipsec.modules.smm_dma
[CHIPSEC] *****************************************************************

iMac Late 2015:

[CHIPSEC] ***************************  SUMMARY  ***************************
[CHIPSEC] Time elapsed          0.007
[CHIPSEC] Modules total         17
[CHIPSEC] Modules failed to run 7:
ERROR: chipsec.modules.common.bios_smi
ERROR: chipsec.modules.common.ia32cfg
ERROR: chipsec.modules.common.smrr
ERROR: chipsec.modules.common.secureboot.variables
ERROR: chipsec.modules.common.uefi.access_uefispec
ERROR: chipsec.modules.common.uefi.s3bootscript
ERROR: chipsec.modules.smm_dma
[CHIPSEC] Modules passed        5:
[+] PASSED: chipsec.modules.common.bios_kbrd_buffer
[+] PASSED: chipsec.modules.common.bios_ts
[+] PASSED: chipsec.modules.common.smm
[+] PASSED: chipsec.modules.common.spi_fdopss
[+] PASSED: chipsec.modules.common.spi_lock
[CHIPSEC] Modules failed        2:
[-] FAILED: chipsec.modules.common.bios_wp
[-] FAILED: chipsec.modules.common.spi_desc
[CHIPSEC] Modules with warnings 0:
[CHIPSEC] Modules skipped 3:
[*] SKIPPED: chipsec.modules.common.rtclock
[*] SKIPPED: chipsec.modules.memconfig
[*] SKIPPED: chipsec.modules.remap
[CHIPSEC] Modules with Exceptions 7:
ERROR: chipsec.modules.common.bios_smi
ERROR: chipsec.modules.common.ia32cfg
ERROR: chipsec.modules.common.smrr
ERROR: chipsec.modules.common.secureboot.variables
ERROR: chipsec.modules.common.uefi.access_uefispec
ERROR: chipsec.modules.common.uefi.s3bootscript
ERROR: chipsec.modules.smm_dma
[CHIPSEC] *****************************************************************

So chipsec.modules.common.bios_wp and chipsec.modules.common.spi_desc failed, here is the details:

[*] running module: chipsec.modules.common.bios_wp
[x][ =======================================================================
[x][ Module: BIOS Region Write Protection
[x][ =======================================================================
[*] BC = 0x00 << BIOS Control (b:d.f 00:31.0 + 0xDC)
    [00] BIOSWE           = 0 << BIOS Write Enable 
    [01] BLE              = 0 << BIOS Lock Enable 
    [02] SRC              = 0 << SPI Read Configuration 
    [04] TSS              = 0 << Top Swap Status 
    [05] SMM_BWP          = 0 << SMM BIOS Write Protection 
[-] BIOS region write protection is disabled!

[*] running module: chipsec.modules.common.spi_desc
[*] Module path: /usr/local/lib/python2.7/site-packages/chipsec/modules/common/spi_desc.pyc
[x][ =======================================================================
[x][ Module: SPI Flash Region Access Control
[x][ =======================================================================
[*] FRAP = 0x0000FFFF << SPI Flash Regions Access Permissions Register (SPIBAR + 0x50)
    [00] BRRA             = FF << BIOS Region Read Access 
    [08] BRWA             = FF << BIOS Region Write Access 
    [16] BMRAG            = 0 << BIOS Master Read Access Grant 
    [24] BMWAG            = 0 << BIOS Master Write Access Grant 
[*] Software access to SPI flash regions: read = 0xFF, write = 0xFF
[-] Software has write access to SPI flash descriptor

[-] FAILED: SPI flash permissions allow SW to write flash descriptor

So... is it just a false positive or is there a much bigger trouble there?

Regards,
S
@c7zero
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c7zero commented Mar 13, 2017

I'm not sure why some modules returned ERROR without the full log (preferably with --verbose option). For the FAILED modules, I'd suggest to update the firmware to the latest revision and re-run

@ghost
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ghost commented Mar 14, 2017

Okay so I re-run with verbose, here is the full logs:

iMac 2015:

[*] Ignoring unsupported platform warning and continue execution
################################################################
##                                                            ##
##  CHIPSEC: Platform Hardware Security Assessment Framework  ##
##                                                            ##
################################################################
[CHIPSEC] Version 1.2.5
[CHIPSEC] Arguments: -i --verbose
[helper] OSX Helper created
Module chipsec.kext loaded successfully
[helper] OSX Helper started/loaded
[CHIPSEC] API mode: using CHIPSEC kernel module API
[pci] reading B/D/F: 0/0/0, offset: 0x00, value: 0x16108086
[*] looking for platform config in '/Users/sabri/Desktop/chipsec-master/chipsec/cfg/common.xml'..
[*] loading common platform config from '/Users/sabri/Desktop/chipsec-master/chipsec/cfg/common.xml'..
[*] loading integrated devices/controllers..
    + HOSTCTRL        : {'fun': '0', 'bus': '0', 'dev': '0x00', 'vid': '0x8086'}
    + PEG10           : {'fun': '0', 'bus': '0', 'dev': '0x01', 'vid': '0x8086'}
    + PEG11           : {'fun': '1', 'bus': '0', 'dev': '0x01', 'vid': '0x8086'}
    + PEG12           : {'fun': '2', 'bus': '0', 'dev': '0x01', 'vid': '0x8086'}
    + IGD             : {'fun': '0', 'bus': '0', 'dev': '0x02', 'vid': '0x8086'}
    + HDAUDIO         : {'fun': '0', 'bus': '0', 'dev': '0x03', 'vid': '0x8086'}
    + XHCI            : {'fun': '0', 'bus': '0', 'dev': '0x14', 'vid': '0x8086'}
    + MEI1            : {'fun': '0', 'bus': '0', 'dev': '0x16', 'vid': '0x8086'}
    + MEI2            : {'fun': '1', 'bus': '0', 'dev': '0x16', 'vid': '0x8086'}
    + IDER            : {'fun': '2', 'bus': '0', 'dev': '0x16', 'vid': '0x8086'}
    + KT              : {'fun': '3', 'bus': '0', 'dev': '0x16', 'vid': '0x8086'}
    + GBE             : {'fun': '0', 'bus': '0', 'dev': '0x19', 'vid': '0x8086'}
    + EHCI2           : {'fun': '0', 'bus': '0', 'dev': '0x1A', 'vid': '0x8086'}
    + AUDIO           : {'fun': '0', 'bus': '0', 'dev': '0x1B', 'vid': '0x8086'}
    + PCIE1           : {'fun': '0', 'bus': '0', 'dev': '0x1C', 'vid': '0x8086'}
    + PCIE2           : {'fun': '1', 'bus': '0', 'dev': '0x1C', 'vid': '0x8086'}
    + PCIE3           : {'fun': '2', 'bus': '0', 'dev': '0x1C', 'vid': '0x8086'}
    + PCIE4           : {'fun': '3', 'bus': '0', 'dev': '0x1C', 'vid': '0x8086'}
    + PCIE5           : {'fun': '4', 'bus': '0', 'dev': '0x1C', 'vid': '0x8086'}
    + PCIE6           : {'fun': '5', 'bus': '0', 'dev': '0x1C', 'vid': '0x8086'}
    + PCIE7           : {'fun': '6', 'bus': '0', 'dev': '0x1C', 'vid': '0x8086'}
    + PCIE8           : {'fun': '7', 'bus': '0', 'dev': '0x1C', 'vid': '0x8086'}
    + EHCI1           : {'fun': '0', 'bus': '0', 'dev': '0x1D', 'vid': '0x8086'}
    + LPC             : {'fun': '0', 'bus': '0', 'dev': '0x1F', 'vid': '0x8086'}
    + SATA1           : {'fun': '2', 'bus': '0', 'dev': '0x1F', 'vid': '0x8086'}
    + SMBUS           : {'fun': '3', 'bus': '0', 'dev': '0x1F', 'vid': '0x8086'}
    + SATA2           : {'fun': '5', 'bus': '0', 'dev': '0x1F', 'vid': '0x8086'}
    + THERMAL         : {'fun': '6', 'bus': '0', 'dev': '0x1F', 'vid': '0x8086'}
[*] loading MMIO BARs..
    + PXPEPBAR        : {'enable_bit': '0', 'bus': '0', 'mask': '0x7FFFFFF000', 'dev': '0', 'width': '8', 'fun': '0', 'size': '0x1000', 'reg': '0x40', 'desc': 'PCI Express Egress Port Register Range'}
    + MCHBAR          : {'enable_bit': '0', 'bus': '0', 'mask': '0x7FFFFF8000', 'dev': '0', 'width': '8', 'fun': '0', 'size': '0x8000', 'reg': '0x48', 'desc': 'Host Memory Mapped Register Range'}
    + MMCFG           : {'enable_bit': '0', 'bus': '0', 'mask': '0x7FFFFFF000', 'dev': '0', 'width': '8', 'fun': '0', 'size': '0x1000', 'reg': '0x60', 'desc': 'PCI Express Register Range'}
    + DMIBAR          : {'enable_bit': '0', 'bus': '0', 'mask': '0x7FFFFFF000', 'dev': '0', 'width': '8', 'fun': '0', 'size': '0x1000', 'reg': '0x68', 'desc': 'Root Complex Register Range'}
    + GTTMMADR        : {'bus': '0', 'mask': '0x7FFFC00000', 'dev': '2', 'width': '8', 'fun': '0', 'reg': '0x10', 'desc': 'Graphics Translation Table Range'}
    + GMADR           : {'bus': '0', 'mask': '0x7FF8000000', 'dev': '2', 'width': '8', 'fun': '0', 'reg': '0x18', 'desc': 'Graphics Memory Range'}
    + HDABAR          : {'bus': '0', 'mask': '0x7FFFFFF000', 'dev': '3', 'width': '8', 'fun': '0', 'size': '0x1000', 'reg': '0x10', 'desc': 'HD Audio Controller Register Range'}
    + HDBAR           : {'bus': '0', 'mask': '0x7FFFFFC000', 'dev': '0x1B', 'width': '8', 'fun': '0', 'size': '0x1000', 'reg': '0x10', 'desc': 'PCH HD Audio Controller Register Range'}
    + RCBA            : {'enable_bit': '0', 'bus': '0', 'mask': '0xFFFFC000', 'dev': '0x1F', 'width': '4', 'fun': '0', 'size': '0x4000', 'reg': '0xF0', 'desc': 'PCH Root Complex Register Range'}
    + SPIBAR          : {'enable_bit': '0', 'bus': '0', 'mask': '0xFFFFC000', 'dev': '0x1F', 'width': '4', 'offset': '0x3800', 'fun': '0', 'size': '0x200', 'reg': '0xF0', 'desc': 'SPI Controller Register Range'}
    + RCBA_RTC        : {'enable_bit': '0', 'bus': '0', 'mask': '0xFFFFC000', 'dev': '0x1F', 'width': '4', 'offset': '0x3400', 'fun': '0', 'size': '0x200', 'reg': '0xF0', 'desc': 'General Control Register Range'}
    + VTBAR           : {'base_field': 'Base', 'enable_field': 'Enable', 'desc': 'Intel VT-d Register Register Range', 'register': 'VTBAR', 'size': '0x1000'}
    + GFXVTBAR        : {'base_field': 'Base', 'enable_field': 'Enable', 'desc': 'Intel Processor Graphics VT-d Register Range', 'register': 'GFXVTBAR', 'size': '0x1000'}
[*] loading I/O BARs..
    + ABASE           : {'size': '0x80', 'register': 'ABASE', 'base_field': 'Base', 'desc': 'ACPI Base Address'}
    + PMBASE          : {'size': '0x80', 'register': 'ABASE', 'base_field': 'Base', 'desc': 'ACPI Base Address'}
    + TCOBASE         : {'base_field': 'Base', 'offset': '0x60', 'desc': 'TCO Base Address', 'register': 'ABASE', 'size': '0x80'}
    + GPIOBASE        : {'size': '0x80', 'register': 'GPIOBASE', 'base_field': 'Base', 'desc': 'GPIO Base Address'}
    + SMBUS_BASE      : {'size': '0x20', 'register': 'SMB_BASE', 'base_field': 'Base', 'desc': 'SMBus Base Address'}
[*] loading memory ranges..
    + Legacy DOS      : {'address': '0x0', 'type': 'dram', 'size': '0x100000'}
    + TPM             : {'address': '0xFED40000', 'type': 'mmio', 'size': '0x10000'}
[*] loading configuration registers..
    + PCI0.0.0_VID    : {'bus': '0', 'dev': '0', 'offset': '0x0', 'fun': '0', 'size': '2', 'type': 'pcicfg', 'desc': 'Vendor ID'}
    + PCI0.0.0_DID    : {'bus': '0', 'dev': '0', 'offset': '0x2', 'fun': '0', 'size': '2', 'type': 'pcicfg', 'desc': 'Device ID'}
    + PCI0.0.0_PXPEPBAR: {'bus': '0', 'dev': '0', 'offset': '0x40', 'fun': '0', 'size': '8', 'type': 'pcicfg', 'desc': 'PCI Express Egress Port Base Address'}
    + PCI0.0.0_MCHBAR : {'bus': '0', 'dev': '0', 'offset': '0x48', 'fun': '0', 'size': '8', 'type': 'pcicfg', 'desc': 'MCH Base Address'}
    + PCI0.0.0_GGC    : {'bus': '0', 'dev': '0', 'offset': '0x50', 'fun': '0', 'FIELDS': {'GGCLOCK': {'bit': '0', 'size': '1', 'desc': 'GGC Lock'}}, 'size': '2', 'type': 'pcicfg', 'desc': 'Graphics Control'}
    + PCI0.0.0_DEVEN  : {'bus': '0', 'dev': '0', 'offset': '0x54', 'fun': '0', 'size': '4', 'type': 'pcicfg', 'desc': 'Device Enables'}
    + PCI0.0.0_PAVPC  : {'bus': '0', 'dev': '0', 'offset': '0x58', 'fun': '0', 'FIELDS': {'PAVPLCK': {'bit': '2', 'size': '1', 'desc': 'Lock'}}, 'size': '4', 'type': 'pcicfg', 'desc': 'PAVP Configuration'}
    + PCI0.0.0_DPR    : {'bus': '0', 'dev': '0', 'offset': '0x5C', 'fun': '0', 'FIELDS': {'LOCK': {'bit': '0', 'size': '1', 'desc': 'Lock'}}, 'size': '4', 'type': 'pcicfg', 'desc': 'DMA Protected Range'}
    + PCI0.0.0_PCIEXBAR: {'bus': '0', 'dev': '0', 'offset': '0x60', 'fun': '0', 'size': '8', 'type': 'pcicfg', 'desc': 'PCIe MMCFG Base Address'}
    + PCI0.0.0_DMIBAR : {'bus': '0', 'dev': '0', 'offset': '0x68', 'fun': '0', 'size': '8', 'type': 'pcicfg', 'desc': 'DMI Base Address'}
    + PCI0.0.0_MESEG_BASE: {'bus': '0', 'dev': '0', 'offset': '0x70', 'fun': '0', 'size': '8', 'type': 'pcicfg', 'desc': 'Manageability Engine Base Address Register'}
    + PCI0.0.0_MESEG_MASK: {'bus': '0', 'dev': '0', 'offset': '0x78', 'fun': '0', 'FIELDS': {'MELCK': {'bit': '10', 'size': '1', 'desc': 'Lock'}}, 'size': '8', 'type': 'pcicfg', 'desc': 'Manageability Engine Limit Address Register'}
    + PCI0.0.0_PAM0   : {'bus': '0', 'dev': '0', 'offset': '0x80', 'fun': '0', 'size': '1', 'type': 'pcicfg', 'desc': 'Programmable Attribute Map 0'}
    + PCI0.0.0_PAM1   : {'bus': '0', 'dev': '0', 'offset': '0x81', 'fun': '0', 'size': '1', 'type': 'pcicfg', 'desc': 'Programmable Attribute Map 1'}
    + PCI0.0.0_PAM2   : {'bus': '0', 'dev': '0', 'offset': '0x82', 'fun': '0', 'size': '1', 'type': 'pcicfg', 'desc': 'Programmable Attribute Map 2'}
    + PCI0.0.0_PAM3   : {'bus': '0', 'dev': '0', 'offset': '0x83', 'fun': '0', 'size': '1', 'type': 'pcicfg', 'desc': 'Programmable Attribute Map 3'}
    + PCI0.0.0_PAM4   : {'bus': '0', 'dev': '0', 'offset': '0x84', 'fun': '0', 'size': '1', 'type': 'pcicfg', 'desc': 'Programmable Attribute Map 4'}
    + PCI0.0.0_PAM5   : {'bus': '0', 'dev': '0', 'offset': '0x85', 'fun': '0', 'size': '1', 'type': 'pcicfg', 'desc': 'Programmable Attribute Map 5'}
    + PCI0.0.0_PAM6   : {'bus': '0', 'dev': '0', 'offset': '0x86', 'fun': '0', 'size': '1', 'type': 'pcicfg', 'desc': 'Programmable Attribute Map 6'}
    + PCI0.0.0_LAC    : {'bus': '0', 'dev': '0', 'offset': '0x87', 'fun': '0', 'size': '1', 'type': 'pcicfg', 'desc': 'Legacy Access Control'}
    + PCI0.0.0_SMRAMC : {'bus': '0', 'dev': '0', 'offset': '0x88', 'fun': '0', 'FIELDS': {'D_CLS': {'bit': '5', 'size': '1', 'desc': 'SMRAM Closed'}, 'D_OPEN': {'bit': '6', 'size': '1', 'desc': 'SMRAM Open'}, 'D_LCK': {'bit': '4', 'size': '1', 'desc': 'SMRAM Locked'}, 'G_SMRAME': {'bit': '3', 'size': '1', 'desc': 'SMRAM Enabled'}, 'C_BASE_SEG': {'bit': '0', 'size': '3', 'desc': 'SMRAM Base Segment = 010b'}}, 'size': '1', 'type': 'pcicfg', 'desc': 'System Management RAM Control'}
    + PCI0.0.0_REMAPBASE: {'bus': '0', 'dev': '0', 'offset': '0x90', 'fun': '0', 'FIELDS': {'LOCK': {'bit': '0', 'size': '1', 'desc': 'Lock'}}, 'size': '8', 'type': 'pcicfg', 'desc': 'Memory Remap Base Address'}
    + PCI0.0.0_REMAPLIMIT: {'bus': '0', 'dev': '0', 'offset': '0x98', 'fun': '0', 'FIELDS': {'LOCK': {'bit': '0', 'size': '1', 'desc': 'Lock'}}, 'size': '8', 'type': 'pcicfg', 'desc': 'Memory Remap Limit Address'}
    + PCI0.0.0_TOM    : {'bus': '0', 'dev': '0', 'offset': '0xA0', 'fun': '0', 'FIELDS': {'LOCK': {'bit': '0', 'size': '1', 'desc': 'Lock'}, 'TOM': {'bit': '20', 'size': '19', 'desc': 'Top of Memory'}}, 'size': '8', 'type': 'pcicfg', 'desc': 'Top of Memory'}
    + PCI0.0.0_TOUUD  : {'bus': '0', 'dev': '0', 'offset': '0xA8', 'fun': '0', 'FIELDS': {'LOCK': {'bit': '0', 'size': '1', 'desc': 'Lock'}, 'TOUUD': {'bit': '20', 'size': '19', 'desc': 'Top of Upper Usable DRAM'}}, 'size': '8', 'type': 'pcicfg', 'desc': 'Top of Upper Usable DRAM'}
    + PCI0.0.0_BDSM   : {'bus': '0', 'dev': '0', 'offset': '0xB0', 'fun': '0', 'FIELDS': {'LOCK': {'bit': '0', 'size': '1', 'desc': 'Lock'}}, 'size': '4', 'type': 'pcicfg', 'desc': 'Base of Graphics Stolen Memory'}
    + PCI0.0.0_BGSM   : {'bus': '0', 'dev': '0', 'offset': '0xB4', 'fun': '0', 'FIELDS': {'BGSM': {'bit': '20', 'size': '12', 'desc': 'Base of GTT Stolen Memory'}, 'LOCK': {'bit': '0', 'size': '1', 'desc': 'Lock'}}, 'size': '4', 'type': 'pcicfg', 'desc': 'Base of GTT Stolen Memory'}
    + PCI0.0.0_TSEGMB : {'bus': '0', 'dev': '0', 'offset': '0xB8', 'fun': '0', 'FIELDS': {'LOCK': {'bit': '0', 'size': '1', 'desc': 'Lock'}, 'TSEGMB': {'bit': '20', 'size': '12', 'desc': 'TSEG Memory Base'}}, 'size': '4', 'type': 'pcicfg', 'desc': 'TSEG Memory Base'}
    + PCI0.0.0_TOLUD  : {'bus': '0', 'dev': '0', 'offset': '0xBC', 'fun': '0', 'FIELDS': {'LOCK': {'bit': '0', 'size': '1', 'desc': 'Lock'}, 'TOLUD': {'bit': '20', 'size': '12', 'desc': 'Top of Lower Usable DRAM'}}, 'size': '4', 'type': 'pcicfg', 'desc': 'Top of Low Usable DRAM'}
    + PCI0.0.0_SKPD   : {'bus': '0', 'dev': '0', 'offset': '0xDC', 'fun': '0', 'size': '4', 'type': 'pcicfg', 'desc': 'Scratchpad Data'}
    + PCI0.0.0_CAPID0_A: {'bus': '0', 'dev': '0', 'offset': '0xE4', 'fun': '0', 'size': '4', 'type': 'pcicfg', 'desc': 'Capabilities A'}
    + PCI0.0.0_CAPID0_B: {'bus': '0', 'dev': '0', 'offset': '0xE8', 'fun': '0', 'size': '4', 'type': 'pcicfg', 'desc': 'Capabilities B'}
    + PCI0.2.0_DID    : {'bus': '0', 'dev': '2', 'offset': '2', 'fun': '0', 'size': '2', 'type': 'pcicfg', 'desc': 'Device Identification Number'}
    + ABASE           : {'bus': '0', 'dev': '0x1F', 'offset': '0x40', 'fun': '0', 'FIELDS': {'Base': {'bit': '7', 'size': '9', 'desc': 'Base Address'}}, 'size': '4', 'type': 'pcicfg', 'desc': 'ACPI Base Address'}
    + GPIOBASE        : {'bus': '0', 'dev': '0x1F', 'offset': '0x48', 'fun': '0', 'FIELDS': {'Base': {'bit': '7', 'size': '9', 'desc': 'Base Address'}}, 'size': '4', 'type': 'pcicfg', 'desc': 'GPIO Base Address'}
    + GC              : {'bus': '0', 'dev': '0x1F', 'offset': '0x4C', 'fun': '0', 'FIELDS': {'EN': {'bit': '4', 'size': '1', 'desc': 'GPIO Enable'}, 'GLE': {'bit': '0', 'size': '1', 'desc': 'GPIO Lockdown Enable'}}, 'size': '1', 'type': 'pcicfg', 'desc': 'GPIO Control'}
    + GEN_PMCON_1     : {'bus': '0', 'dev': '0x1f', 'offset': '0xA0', 'fun': '0', 'FIELDS': {'SMI_LOCK': {'bit': '4', 'desc': '', 'size': '1'}}, 'size': '2', 'type': 'pcicfg', 'desc': 'General PM Configuration 1'}
    + BC              : {'bus': '0', 'dev': '0x1F', 'offset': '0xDC', 'fun': '0', 'FIELDS': {'BLE': {'bit': '1', 'size': '1', 'desc': 'BIOS Lock Enable'}, 'SRC': {'bit': '2', 'size': '2', 'desc': 'SPI Read Configuration'}, 'SMM_BWP': {'bit': '5', 'size': '1', 'desc': 'SMM BIOS Write Protection'}, 'BIOSWE': {'bit': '0', 'size': '1', 'desc': 'BIOS Write Enable'}, 'TSS': {'bit': '4', 'size': '1', 'desc': 'Top Swap Status'}}, 'size': '1', 'type': 'pcicfg', 'desc': 'BIOS Control'}
    + SMBUS_VID       : {'bus': '0', 'dev': '0x1F', 'offset': '0x00', 'fun': '3', 'size': '2', 'type': 'pcicfg', 'desc': 'VID'}
    + SMBUS_DID       : {'bus': '0', 'dev': '0x1F', 'offset': '0x02', 'fun': '3', 'size': '2', 'type': 'pcicfg', 'desc': 'DID'}
    + SMBUS_CMD       : {'bus': '0', 'dev': '0x1F', 'offset': '0x04', 'fun': '3', 'size': '2', 'type': 'pcicfg', 'desc': 'CMD'}
    + SMB_BASE        : {'bus': '0', 'dev': '0x1F', 'offset': '0x20', 'fun': '3', 'FIELDS': {'Base': {'bit': '5', 'size': '11', 'desc': 'Base Address'}}, 'size': '4', 'type': 'pcicfg', 'desc': 'SMBus Base Address'}
    + SMBUS_HCFG      : {'bus': '0', 'dev': '0x1F', 'offset': '0x40', 'fun': '3', 'FIELDS': {'I2C_EN': {'bit': '2', 'desc': '', 'size': '2'}, 'SPD_WD': {'bit': '4', 'desc': '', 'size': '1'}, 'SSRESET': {'bit': '3', 'desc': '', 'size': '1'}, 'SMB_SMI_EN': {'bit': '1', 'desc': '', 'size': '1'}, 'HST_EN': {'bit': '0', 'desc': '', 'size': '1'}}, 'size': '1', 'type': 'pcicfg', 'desc': 'Host Configuration'}
    + BFPR            : {'bar': 'SPIBAR', 'offset': '0x00', 'FIELDS': {'PRL': {'bit': '16', 'size': '13', 'desc': 'BIOS Flash Primary Region Limit'}, 'PRB': {'bit': '0', 'size': '13', 'desc': 'BIOS Flash Primary Region Base'}}, 'desc': 'BIOS Flash Primary Region Register (= FREG1)', 'type': 'mmio', 'size': '4'}
    + HSFS            : {'bar': 'SPIBAR', 'offset': '0x04', 'FIELDS': {'SCIP': {'bit': '5', 'size': '1', 'desc': 'SPI cycle in progress'}, 'FLOCKDN': {'bit': '15', 'size': '1', 'desc': 'Flash Configuration Lock-Down'}, 'FCERR': {'bit': '1', 'size': '1', 'desc': 'Flash Cycle Error'}, 'BERASE': {'bit': '3', 'size': '2', 'desc': 'Block/Sector Erase Size'}, 'FDV': {'bit': '14', 'size': '1', 'desc': 'Flash Descriptor Valid'}, 'FDOPSS': {'bit': '13', 'size': '1', 'desc': 'Flash Descriptor Override Pin-Strap Status'}, 'FDONE': {'bit': '0', 'size': '1', 'desc': 'Flash Cycle Done'}, 'AEL': {'bit': '2', 'size': '1', 'desc': 'Access Error Log'}}, 'desc': 'Hardware Sequencing Flash Status Register', 'type': 'mmio', 'size': '2'}
    + HSFC            : {'bar': 'SPIBAR', 'offset': '0x06', 'FIELDS': {'FSMIE': {'bit': '15', 'size': '1', 'desc': 'Flash SPI SMI Enable'}, 'FCYCLE': {'bit': '1', 'size': '2', 'desc': 'Flash Cycle'}, 'FGO': {'bit': '0', 'size': '1', 'desc': 'Flash Cycle GO'}, 'FDBC': {'bit': '8', 'size': '6', 'desc': 'Flash Data Byte Count, Count = FDBC + 1'}}, 'desc': 'Hardware Sequencing Flash Control Register', 'type': 'mmio', 'size': '2'}
    + FADDR           : {'bar': 'SPIBAR', 'offset': '0x08', 'desc': 'Flash Address Register', 'type': 'mmio', 'size': '4'}
    + FDATA0          : {'bar': 'SPIBAR', 'offset': '0x10', 'desc': 'Flash Data 0', 'type': 'mmio', 'size': '4'}
    + FDATA1          : {'bar': 'SPIBAR', 'offset': '0x14', 'desc': 'Flash Data 1', 'type': 'mmio', 'size': '4'}
    + FDATA2          : {'bar': 'SPIBAR', 'offset': '0x18', 'desc': 'Flash Data 2', 'type': 'mmio', 'size': '4'}
    + FDATA3          : {'bar': 'SPIBAR', 'offset': '0x1C', 'desc': 'Flash Data 3', 'type': 'mmio', 'size': '4'}
    + FDATA4          : {'bar': 'SPIBAR', 'offset': '0x20', 'desc': 'Flash Data 4', 'type': 'mmio', 'size': '4'}
    + FDATA5          : {'bar': 'SPIBAR', 'offset': '0x24', 'desc': 'Flash Data 5', 'type': 'mmio', 'size': '4'}
    + FDATA6          : {'bar': 'SPIBAR', 'offset': '0x28', 'desc': 'Flash Data 6', 'type': 'mmio', 'size': '4'}
    + FDATA7          : {'bar': 'SPIBAR', 'offset': '0x2C', 'desc': 'Flash Data 7', 'type': 'mmio', 'size': '4'}
    + FDATA8          : {'bar': 'SPIBAR', 'offset': '0x30', 'desc': 'Flash Data 8', 'type': 'mmio', 'size': '4'}
    + FDATA9          : {'bar': 'SPIBAR', 'offset': '0x34', 'desc': 'Flash Data 9', 'type': 'mmio', 'size': '4'}
    + FDATA10         : {'bar': 'SPIBAR', 'offset': '0x38', 'desc': 'Flash Data 10', 'type': 'mmio', 'size': '4'}
    + FDATA11         : {'bar': 'SPIBAR', 'offset': '0x3C', 'desc': 'Flash Data 11', 'type': 'mmio', 'size': '4'}
    + FDATA12         : {'bar': 'SPIBAR', 'offset': '0x40', 'desc': 'Flash Data 12', 'type': 'mmio', 'size': '4'}
    + FDATA13         : {'bar': 'SPIBAR', 'offset': '0x44', 'desc': 'Flash Data 13', 'type': 'mmio', 'size': '4'}
    + FDATA14         : {'bar': 'SPIBAR', 'offset': '0x48', 'desc': 'Flash Data 14', 'type': 'mmio', 'size': '4'}
    + FDATA15         : {'bar': 'SPIBAR', 'offset': '0x4C', 'desc': 'Flash Data 15', 'type': 'mmio', 'size': '4'}
    + FRAP            : {'bar': 'SPIBAR', 'offset': '0x50', 'FIELDS': {'BMRAG': {'bit': '16', 'size': '8', 'desc': 'BIOS Master Read Access Grant'}, 'BMWAG': {'bit': '24', 'size': '8', 'desc': 'BIOS Master Write Access Grant'}, 'BRWA': {'bit': '8', 'size': '8', 'desc': 'BIOS Region Write Access'}, 'BRRA': {'bit': '0', 'size': '8', 'desc': 'BIOS Region Read Access'}}, 'desc': 'SPI Flash Regions Access Permissions Register', 'type': 'mmio', 'size': '4'}
    + FREG0_FLASHD    : {'bar': 'SPIBAR', 'offset': '0x54', 'FIELDS': {'RL': {'bit': '16', 'size': '12', 'desc': 'Region Limit'}, 'RB': {'bit': '0', 'size': '12', 'desc': 'Region Base'}}, 'desc': 'Flash Region 0 (Flash Descriptor)', 'type': 'mmio', 'size': '4'}
    + FREG1_BIOS      : {'bar': 'SPIBAR', 'offset': '0x58', 'FIELDS': {'RL': {'bit': '16', 'size': '12', 'desc': 'Region Limit'}, 'RB': {'bit': '0', 'size': '12', 'desc': 'Region Base'}}, 'desc': 'Flash Region 1 (BIOS)', 'type': 'mmio', 'size': '4'}
    + FREG2_ME        : {'bar': 'SPIBAR', 'offset': '0x5C', 'FIELDS': {'RL': {'bit': '16', 'size': '12', 'desc': 'Region Limit'}, 'RB': {'bit': '0', 'size': '12', 'desc': 'Region Base'}}, 'desc': 'Flash Region 2 (ME)', 'type': 'mmio', 'size': '4'}
    + FREG3_GBE       : {'bar': 'SPIBAR', 'offset': '0x60', 'FIELDS': {'RL': {'bit': '16', 'size': '12', 'desc': 'Region Limit'}, 'RB': {'bit': '0', 'size': '12', 'desc': 'Region Base'}}, 'desc': 'Flash Region 3 (GBe)', 'type': 'mmio', 'size': '4'}
    + FREG4_PD        : {'bar': 'SPIBAR', 'offset': '0x64', 'FIELDS': {'RL': {'bit': '16', 'size': '12', 'desc': 'Region Limit'}, 'RB': {'bit': '0', 'size': '12', 'desc': 'Region Base'}}, 'desc': 'Flash Region 4 (Platform Data)', 'type': 'mmio', 'size': '4'}
    + FREG5           : {'bar': 'SPIBAR', 'offset': '0x68', 'FIELDS': {'RL': {'bit': '16', 'size': '12', 'desc': 'Region Limit'}, 'RB': {'bit': '0', 'size': '12', 'desc': 'Region Base'}}, 'desc': 'Flash Region 5', 'type': 'mmio', 'size': '4'}
    + FREG6           : {'bar': 'SPIBAR', 'offset': '0x6C', 'FIELDS': {'RL': {'bit': '16', 'size': '12', 'desc': 'Region Limit'}, 'RB': {'bit': '0', 'size': '12', 'desc': 'Region Base'}}, 'desc': 'Flash Region 6', 'type': 'mmio', 'size': '4'}
    + PR0             : {'bar': 'SPIBAR', 'offset': '0x74', 'FIELDS': {'PRL': {'bit': '16', 'size': '13', 'desc': 'Protected Range Limit'}, 'RPE': {'bit': '15', 'size': '1', 'desc': 'Read Protection Enabled'}, 'WPE': {'bit': '31', 'size': '1', 'desc': 'Write Protection Enabled'}, 'PRB': {'bit': '0', 'size': '13', 'desc': 'Protected Range Base'}}, 'desc': 'Protected Range 0', 'type': 'mmio', 'size': '4'}
    + PR1             : {'bar': 'SPIBAR', 'offset': '0x78', 'FIELDS': {'PRL': {'bit': '16', 'size': '13', 'desc': 'Protected Range Limit'}, 'RPE': {'bit': '15', 'size': '1', 'desc': 'Read Protection Enabled'}, 'WPE': {'bit': '31', 'size': '1', 'desc': 'Write Protection Enabled'}, 'PRB': {'bit': '0', 'size': '13', 'desc': 'Protected Range Base'}}, 'desc': 'Protected Range 1', 'type': 'mmio', 'size': '4'}
    + PR2             : {'bar': 'SPIBAR', 'offset': '0x7C', 'FIELDS': {'PRL': {'bit': '16', 'size': '13', 'desc': 'Protected Range Limit'}, 'RPE': {'bit': '15', 'size': '1', 'desc': 'Read Protection Enabled'}, 'WPE': {'bit': '31', 'size': '1', 'desc': 'Write Protection Enabled'}, 'PRB': {'bit': '0', 'size': '13', 'desc': 'Protected Range Base'}}, 'desc': 'Protected Range 2', 'type': 'mmio', 'size': '4'}
    + PR3             : {'bar': 'SPIBAR', 'offset': '0x80', 'FIELDS': {'PRL': {'bit': '16', 'size': '13', 'desc': 'Protected Range Limit'}, 'RPE': {'bit': '15', 'size': '1', 'desc': 'Read Protection Enabled'}, 'WPE': {'bit': '31', 'size': '1', 'desc': 'Write Protection Enabled'}, 'PRB': {'bit': '0', 'size': '13', 'desc': 'Protected Range Base'}}, 'desc': 'Protected Range 3', 'type': 'mmio', 'size': '4'}
    + PR4             : {'bar': 'SPIBAR', 'offset': '0x84', 'FIELDS': {'PRL': {'bit': '16', 'size': '13', 'desc': 'Protected Range Limit'}, 'RPE': {'bit': '15', 'size': '1', 'desc': 'Read Protection Enabled'}, 'WPE': {'bit': '31', 'size': '1', 'desc': 'Write Protection Enabled'}, 'PRB': {'bit': '0', 'size': '13', 'desc': 'Protected Range Base'}}, 'desc': 'Protected Range 4', 'type': 'mmio', 'size': '4'}
    + PREOP           : {'bar': 'SPIBAR', 'offset': '0x94', 'FIELDS': {'PREOP0': {'bit': '0', 'size': '8', 'desc': 'Prefix Opcode 0'}, 'PREOP1': {'bit': '8', 'size': '8', 'desc': 'Prefix Opcode 1'}}, 'desc': 'Prefix Opcode Configuration Register', 'type': 'mmio', 'size': '2'}
    + OPTYPE          : {'bar': 'SPIBAR', 'offset': '0x96', 'FIELDS': {'OPTYPE0': {'bit': '0', 'size': '2', 'desc': 'Opcode Type 0'}, 'OPTYPE1': {'bit': '2', 'size': '2', 'desc': 'Opcode Type 1'}, 'OPTYPE2': {'bit': '4', 'size': '2', 'desc': 'Opcode Type 2'}, 'OPTYPE3': {'bit': '6', 'size': '2', 'desc': 'Opcode Type 3'}, 'OPTYPE4': {'bit': '8', 'size': '2', 'desc': 'Opcode Type 4'}, 'OPTYPE5': {'bit': '10', 'size': '2', 'desc': 'Opcode Type 5'}, 'OPTYPE6': {'bit': '12', 'size': '2', 'desc': 'Opcode Type 6'}, 'OPTYPE7': {'bit': '14', 'size': '2', 'desc': 'Opcode Type 7'}}, 'desc': 'Opcode Type Configuration Register', 'type': 'mmio', 'size': '2'}
    + OPMENU          : {'bar': 'SPIBAR', 'offset': '0x98', 'FIELDS': {'OPCODE1': {'bit': '8', 'size': '8', 'desc': 'Allowable Opcode 1'}, 'OPCODE0': {'bit': '0', 'size': '8', 'desc': 'Allowable Opcode 0'}, 'OPCODE3': {'bit': '24', 'size': '8', 'desc': 'Allowable Opcode 3'}, 'OPCODE2': {'bit': '16', 'size': '8', 'desc': 'Allowable Opcode 2'}, 'OPCODE5': {'bit': '40', 'size': '8', 'desc': 'Allowable Opcode 5'}, 'OPCODE4': {'bit': '32', 'size': '8', 'desc': 'Allowable Opcode 4'}, 'OPCODE7': {'bit': '56', 'size': '8', 'desc': 'Allowable Opcode 7'}, 'OPCODE6': {'bit': '48', 'size': '8', 'desc': 'Allowable Opcode 6'}}, 'desc': 'Opcode Menu Configuration Register', 'type': 'mmio', 'size': '8'}
    + OPMENU_LO       : {'bar': 'SPIBAR', 'offset': '0x98', 'FIELDS': {'OPCODE1': {'bit': '8', 'size': '8', 'desc': 'Allowable Opcode 1'}, 'OPCODE0': {'bit': '0', 'size': '8', 'desc': 'Allowable Opcode 0'}, 'OPCODE3': {'bit': '24', 'size': '8', 'desc': 'Allowable Opcode 3'}, 'OPCODE2': {'bit': '16', 'size': '8', 'desc': 'Allowable Opcode 2'}}, 'desc': 'Opcode Menu Configuration Register Low', 'type': 'mmio', 'size': '4'}
    + OPMENU_HI       : {'bar': 'SPIBAR', 'offset': '0x9C', 'FIELDS': {'OPCODE5': {'bit': '8', 'size': '8', 'desc': 'Allowable Opcode 5'}, 'OPCODE4': {'bit': '0', 'size': '8', 'desc': 'Allowable Opcode 4'}, 'OPCODE7': {'bit': '24', 'size': '8', 'desc': 'Allowable Opcode 7'}, 'OPCODE6': {'bit': '16', 'size': '8', 'desc': 'Allowable Opcode 6'}}, 'desc': 'Opcode Menu Configuration Register High', 'type': 'mmio', 'size': '4'}
    + FDOC            : {'bar': 'SPIBAR', 'offset': '0xB0', 'FIELDS': {'FDSS': {'bit': '12', 'size': '3', 'desc': 'Flash Descriptor Section Select'}, 'FDSI': {'bit': '2', 'size': '10', 'desc': 'Flash Descriptor Section Index'}}, 'desc': 'Flash Descriptor Observability Control Register', 'type': 'mmio', 'size': '4'}
    + FDOD            : {'bar': 'SPIBAR', 'offset': '0xB4', 'FIELDS': {'FDSD': {'bit': '0', 'size': '32', 'desc': 'Flash Descriptor Section Data'}}, 'desc': 'Flash Descriptor Observability Data Register', 'type': 'mmio', 'size': '4'}
    + LVSCC           : {'bar': 'SPIBAR', 'offset': '0xC4', 'FIELDS': {'LWSR': {'bit': '3', 'size': '1', 'desc': 'Lower Write Status Required'}, 'VCL': {'bit': '23', 'size': '1', 'desc': 'Vendor Component Lock'}, 'LEO': {'bit': '8', 'size': '8', 'desc': 'Lower Erase Opcode'}, 'LBES': {'bit': '0', 'size': '2', 'desc': 'Lower Block/Sector Erase Size'}, 'LWG': {'bit': '2', 'size': '1', 'desc': 'Lower Write Granularity'}, 'LWEWS': {'bit': '4', 'size': '1', 'desc': 'Write Enable on Write Status'}}, 'desc': 'Host Lower Vendor Specific Component Capabilities', 'type': 'mmio', 'size': '4'}
    + UVSCC           : {'bar': 'SPIBAR', 'offset': '0xC8', 'FIELDS': {'UBES': {'bit': '0', 'size': '2', 'desc': 'Upper Block/Sector Erase Size'}, 'UEO': {'bit': '8', 'size': '8', 'desc': 'Upper Erase Opcode'}, 'UWG': {'bit': '2', 'size': '1', 'desc': 'Upper Write Granularity'}, 'UWEWS': {'bit': '4', 'size': '1', 'desc': 'Write Enable on Write Status'}, 'UWSR': {'bit': '3', 'size': '1', 'desc': 'Upper Write Status Required'}}, 'desc': 'Host Upper Vendor Specific Component Capabilities', 'type': 'mmio', 'size': '4'}
    + FLMAP0          : {'bar': 'FDBAR', 'offset': '0x14', 'FIELDS': {'FRBA': {'bit': '16', 'size': '8', 'desc': 'Flash Region Base Address'}, 'NR': {'bit': '24', 'size': '3', 'desc': 'Number of Regions'}, 'NC': {'bit': '8', 'size': '2', 'desc': 'Number of Components'}, 'FCBA': {'bit': '0', 'size': '8', 'desc': 'Flash Component Base Address'}}, 'desc': 'Flash Map 0 Register', 'type': 'mmio', 'size': '4'}
    + FLMAP1          : {'bar': 'FDBAR', 'offset': '0x18', 'FIELDS': {'FMBA': {'bit': '0', 'size': '8', 'desc': 'Flash Master Base Address'}, 'FPSBA': {'bit': '16', 'size': '8', 'desc': 'Flash PCH Strap Base Address'}, 'NM': {'bit': '8', 'size': '2', 'desc': 'Number of Masters'}, 'PSL': {'bit': '24', 'size': '8', 'desc': 'PCH Strap Length'}}, 'desc': 'Flash Map 1 Register', 'type': 'mmio', 'size': '4'}
    + FLMAP2          : {'bar': 'FDBAR', 'offset': '0x1C', 'FIELDS': {'ICCRIBA': {'bit': '16', 'size': '8', 'desc': 'ICC Register Init Base Address'}, 'CPUSL': {'bit': '8', 'size': '8', 'desc': 'Processor Strap Length'}, 'FCPUSBA': {'bit': '0', 'size': '8', 'desc': 'Flash CPU Strap Base Address'}}, 'desc': 'Flash Map 2 Register', 'type': 'mmio', 'size': '4'}
    + FLREG0          : {'bar': 'FRBA', 'offset': '0x0', 'FIELDS': {'RL': {'bit': '16', 'size': '13', 'desc': 'Region Limit'}, 'RB': {'bit': '0', 'size': '13', 'desc': 'Region Base'}}, 'desc': 'Flash Region 0 (Flash Descriptor) Register', 'type': 'mmio', 'size': '4'}
    + FLREG1          : {'bar': 'FRBA', 'offset': '0x4', 'FIELDS': {'RL': {'bit': '16', 'size': '13', 'desc': 'Region Limit'}, 'RB': {'bit': '0', 'size': '13', 'desc': 'Region Base'}}, 'desc': 'Flash Region 1 (BIOS) Register', 'type': 'mmio', 'size': '4'}
    + FLREG2          : {'bar': 'FRBA', 'offset': '0x8', 'FIELDS': {'RL': {'bit': '16', 'size': '13', 'desc': 'Region Limit'}, 'RB': {'bit': '0', 'size': '13', 'desc': 'Region Base'}}, 'desc': 'Flash Region 2 (Intel ME) Register', 'type': 'mmio', 'size': '4'}
    + FLREG3          : {'bar': 'FRBA', 'offset': '0xC', 'FIELDS': {'RL': {'bit': '16', 'size': '13', 'desc': 'Region Limit'}, 'RB': {'bit': '0', 'size': '13', 'desc': 'Region Base'}}, 'desc': 'Flash Region 3 (GBe) Register', 'type': 'mmio', 'size': '4'}
    + FLREG4          : {'bar': 'FRBA', 'offset': '0x10', 'FIELDS': {'RL': {'bit': '16', 'size': '13', 'desc': 'Region Limit'}, 'RB': {'bit': '0', 'size': '13', 'desc': 'Region Base'}}, 'desc': 'Flash Region 4 (Platform Data) Register', 'type': 'mmio', 'size': '4'}
    + FLMSTR1         : {'bar': 'FMBA', 'offset': '0x0', 'FIELDS': {'MRRA': {'bit': '16', 'size': '8', 'desc': 'Master Region Read Access'}, 'MRWA': {'bit': '24', 'size': '8', 'desc': 'Master Region Write Access'}}, 'desc': 'Flash Master 1', 'type': 'mmio', 'size': '4'}
    + RC              : {'bar': 'RCBA', 'offset': '0x3400', 'FIELDS': {'UE': {'bit': '2', 'size': '1', 'desc': 'Upper 128 Byte Enable'}, 'UL': {'bit': '4', 'size': '1', 'desc': 'Upper 128 Byte Lock'}, 'LL': {'bit': '3', 'size': '1', 'desc': 'Lower 128 Byte Lock'}}, 'desc': 'RTC Configuration', 'type': 'mmio', 'size': '4'}
    + GCS             : {'bar': 'RCBA', 'offset': '0x3410', 'FIELDS': {'BILD': {'bit': '0', 'size': '1', 'desc': 'BIOS Interface Lock Down'}, 'BBS': {'bit': '10', 'size': '2', 'desc': 'Boot BIOS Straps'}}, 'desc': 'General Control and Status', 'type': 'mmio', 'size': '4'}
    + RC              : {'bar': 'RCBA', 'offset': '0x3400', 'FIELDS': {'UE': {'bit': '2', 'size': '1', 'desc': 'Upper 128 Byte Enable'}, 'UL': {'bit': '4', 'size': '1', 'desc': 'Upper 128 Byte Lock'}, 'LL': {'bit': '3', 'size': '1', 'desc': 'Lower 128 Byte Lock'}}, 'desc': 'RTC Configuration', 'type': 'mmio', 'size': '4'}
    + BUC             : {'bar': 'RCBA', 'offset': '0x3414', 'FIELDS': {'TS': {'bit': '0', 'size': '1', 'desc': 'Top Swap'}}, 'desc': 'Backed Up Control', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR        : {'bar': 'MCHBAR', 'offset': '0x5400', 'FIELDS': {'Base': {'bit': '12', 'size': '27', 'desc': 'GFX VTD Base Address'}, 'Enable': {'bit': '0', 'size': '1', 'desc': 'Enable'}}, 'desc': 'Processor Graphics VT-d MMIO Base Address', 'type': 'mmio', 'size': '8'}
    + VTBAR           : {'bar': 'MCHBAR', 'offset': '0x5410', 'FIELDS': {'Base': {'bit': '12', 'size': '27', 'desc': 'VTD Base Address'}, 'Enable': {'bit': '0', 'size': '1', 'desc': 'Enable'}}, 'desc': 'VT-d MMIO Base Address', 'type': 'mmio', 'size': '8'}
    + RST_CNT         : {'FIELDS': {'FULL_RST': {'bit': '3', 'size': '1', 'desc': 'Full Reset'}, 'SYS_RST': {'bit': '1', 'size': '1', 'desc': 'System Reset'}, 'RST_CPU': {'bit': '2', 'size': '1', 'desc': 'Reset Processor'}}, 'desc': 'Reset Control', 'type': 'io', 'port': '0xCF9', 'size': '1'}
    + PM1_STS         : {'bar': 'ABASE', 'offset': '0x0', 'FIELDS': {'RTC_STS': {'bit': '10', 'size': '1', 'desc': 'RTC Status'}, 'PWRBTN_STS': {'bit': '8', 'size': '1', 'desc': 'Power Button Status'}, 'WAK_STS': {'bit': '15', 'size': '1', 'desc': 'Wake Status'}, 'TMROF_STS': {'bit': '0', 'size': '1', 'desc': 'Timer Overflow Status'}, 'GBL_STS': {'bit': '5', 'size': '1', 'desc': 'Global Status'}, 'PWRBTNOR_STS': {'bit': '11', 'size': '1', 'desc': 'Power Button Override Status'}, 'PCIEXPWAK_STS': {'bit': '14', 'size': '1', 'desc': 'PCI Express Wake Status'}, 'BM_STS': {'bit': '4', 'size': '1', 'desc': 'Bus Master Status'}}, 'desc': 'PM1 Status', 'type': 'iobar', 'size': '2'}
    + PM1_EN          : {'bar': 'ABASE', 'offset': '0x2', 'FIELDS': {'PCIEXPWAK_DIS': {'bit': '14', 'size': '1', 'desc': 'PCI Express Wake Disable'}, 'PWRBTN_EN': {'bit': '8', 'size': '1', 'desc': 'Power Button Enable'}, 'GBL_EN': {'bit': '5', 'size': '1', 'desc': 'Global Enable'}, 'TMROF_EN': {'bit': '0', 'size': '1', 'desc': 'Timer Overflow Interrupt Enable'}, 'RTC_EN': {'bit': '10', 'size': '1', 'desc': 'RTC Event Enable'}}, 'desc': 'PM1 Enable', 'type': 'iobar', 'size': '2'}
    + PM1_CNT         : {'bar': 'ABASE', 'offset': '0x4', 'FIELDS': {'SLP_EN': {'bit': '13', 'size': '1', 'desc': 'Sleep Enable'}, 'SLP_TYP': {'bit': '10', 'size': '3', 'desc': 'Sleep Type'}, 'BM_RLD': {'bit': '1', 'size': '1', 'desc': 'Bus Master Reload'}, 'GBL_RLS': {'bit': '2', 'size': '1', 'desc': 'Global Release'}, 'SCI_EN': {'bit': '0', 'size': '1', 'desc': 'SCI Enable'}}, 'desc': 'PM1 Control', 'type': 'iobar', 'size': '4'}
    + PM1_TMR         : {'bar': 'ABASE', 'offset': '0x8', 'FIELDS': {'TMR_VAL': {'bit': '0', 'size': '24', 'desc': 'Timer Value'}}, 'desc': 'PM1 Timer', 'type': 'iobar', 'size': '4'}
    + SMI_EN          : {'bar': 'ABASE', 'offset': '0x30', 'FIELDS': {'APMC_EN': {'bit': '5', 'desc': '', 'size': '1'}, 'ME_SMI_EN': {'bit': '30', 'desc': '', 'size': '1'}, 'SWSMI_TMR_EN': {'bit': '6', 'desc': '', 'size': '1'}, 'LEGACY_USB_EN': {'bit': '3', 'desc': '', 'size': '1'}, 'BIOS_EN': {'bit': '2', 'desc': '', 'size': '1'}, 'PERIODIC_EN': {'bit': '14', 'desc': '', 'size': '1'}, 'xHCI_SMI_EN': {'bit': '31', 'desc': '', 'size': '1'}, 'MCSMI_EN': {'bit': '11', 'desc': '', 'size': '1'}, 'INTEL_USB2_EN': {'bit': '18', 'desc': '', 'size': '1'}, 'GBL_SMI_EN': {'bit': '0', 'desc': '', 'size': '1'}, 'EOS': {'bit': '1', 'desc': '', 'size': '1'}, 'LEGACY_USB2_EN': {'bit': '17', 'desc': '', 'size': '1'}, 'TCO_EN': {'bit': '13', 'desc': '', 'size': '1'}, 'BIOS_RLS': {'bit': '7', 'desc': '', 'size': '1'}, 'GPIO_UNLOCK_SMI_EN': {'bit': '27', 'desc': '', 'size': '1'}, 'SLP_SMI_EN': {'bit': '4', 'desc': '', 'size': '1'}}, 'desc': 'SMI Control and Enable', 'type': 'iobar', 'size': '4'}
    + TCO1_CNT        : {'bar': 'ABASE', 'offset': '0x68', 'FIELDS': {'TCO_LOCK': {'bit': '12', 'desc': '', 'size': '1'}}, 'desc': 'TCO1 Control', 'type': 'iobar', 'size': '2'}
    + SMBUS_HST_STS   : {'bar': 'SMBUS_BASE', 'offset': '0x00', 'FIELDS': {'BUSY': {'bit': '0', 'size': '1', 'desc': 'SMBus Busy'}, 'DEV_ERR': {'bit': '2', 'size': '1', 'desc': 'Device Error'}, 'INUSE_STS': {'bit': '6', 'size': '1', 'desc': 'InUse Semaphore Status'}, 'DS': {'bit': '7', 'size': '1', 'desc': 'Done Status'}, 'FAILED': {'bit': '4', 'size': '1', 'desc': 'SMBus Error/Failed'}, 'BUS_ERR': {'bit': '3', 'size': '1', 'desc': 'Bus Error'}, 'INTR': {'bit': '1', 'size': '1', 'desc': 'Interrupt'}, 'SMBALERT_STS': {'bit': '5', 'size': '1', 'desc': 'SMBALERT# Signal Status'}}, 'desc': 'SMBus Host Status', 'type': 'iobar', 'size': '1'}
    + SMBUS_HST_CNT   : {'bar': 'SMBUS_BASE', 'offset': '0x02', 'FIELDS': {'PEC_EN': {'bit': '7', 'size': '1', 'desc': 'Packet Error Checking Enable'}, 'START': {'bit': '6', 'size': '1', 'desc': 'Start/Trigger'}, 'KILL': {'bit': '1', 'size': '1', 'desc': 'Kill'}, 'SMB_CMD': {'bit': '2', 'size': '3', 'desc': 'Command'}, 'LAST_BYTE': {'bit': '5', 'size': '1', 'desc': 'Last Byte (for Block Read commands)'}, 'INTREN': {'bit': '0', 'size': '1', 'desc': 'Interrupt Enable'}}, 'desc': 'SMBus Host Control', 'type': 'iobar', 'size': '1'}
    + SMBUS_HST_CMD   : {'bar': 'SMBUS_BASE', 'offset': '0x03', 'FIELDS': {'DataOffset': {'bit': '0', 'size': '8', 'desc': 'Command Data'}}, 'desc': 'SMBus Host Command', 'type': 'iobar', 'size': '1'}
    + SMBUS_HST_SLVA  : {'bar': 'SMBUS_BASE', 'offset': '0x04', 'FIELDS': {'RW': {'bit': '0', 'size': '1', 'desc': 'Read/Write Command'}, 'Address': {'bit': '1', 'size': '7', 'desc': 'Slave Address'}}, 'desc': 'SMBus Host Slave Address', 'type': 'iobar', 'size': '1'}
    + SMBUS_HST_D0    : {'bar': 'SMBUS_BASE', 'offset': '0x05', 'FIELDS': {'Data': {'bit': '0', 'size': '8', 'desc': 'Data0/Count'}}, 'desc': 'SMBus Host Data 0', 'type': 'iobar', 'size': '1'}
    + SMBUS_HST_D1    : {'bar': 'SMBUS_BASE', 'offset': '0x06', 'FIELDS': {'Data': {'bit': '0', 'size': '8', 'desc': 'Data1'}}, 'desc': 'SMBus Host Data 1', 'type': 'iobar', 'size': '1'}
    + IA32_BIOS_SIGN_ID: {'FIELDS': {'Microcode': {'bit': '32', 'size': '32', 'desc': 'Microcode update signature'}}, 'msr': '0x8B', 'desc': 'Microcode Update Signature Register', 'type': 'msr', 'size': '0x4'}
    + IA32_SMRR_PHYSBASE: {'FIELDS': {'Type': {'bit': '0', 'size': '8', 'desc': 'SMRR memory type'}, 'PhysBase': {'bit': '12', 'size': '20', 'desc': 'SMRR physical base address'}}, 'msr': '0x1F2', 'desc': 'SMRR Base Address MSR', 'type': 'msr', 'size': '0x4'}
    + IA32_SMRR_PHYSMASK: {'FIELDS': {'PhysMask': {'bit': '12', 'size': '20', 'desc': 'SMRR address range mask'}, 'Valid': {'bit': '11', 'size': '1', 'desc': 'SMRR valid'}}, 'msr': '0x1F3', 'desc': 'SMRR Range Mask MSR', 'type': 'msr', 'size': '0x4'}
    + MTRRCAP         : {'FIELDS': {'SMRR': {'bit': '11', 'size': '1', 'desc': 'SMRR Supported'}}, 'msr': '0xFE', 'desc': 'MTRR Capabilities MSR', 'type': 'msr', 'size': '0x4'}
    + IA32_FEATURE_CONTROL: {'FIELDS': {'SENTER_LOCAL_EN': {'bit': '8', 'size': '7', 'desc': 'SENTER Local Functions Enable'}, 'SENTER_GLOBAL_EN': {'bit': '15', 'size': '1', 'desc': 'SENTER Global Enable'}, 'LOCK': {'bit': '0', 'size': '1', 'desc': 'Lock'}, 'LMCE_ON': {'bit': '20', 'size': '1', 'desc': 'Turn Local Machine Check On'}, 'EN_VMX_INSIDE_SMX': {'bit': '1', 'size': '1', 'desc': 'Enable VMX inside SMX operation'}, 'EN_VMX_OUTSIDE_SMX': {'bit': '2', 'size': '1', 'desc': 'Enable VMX outside SMX operation'}, 'Reserved1': {'bit': '16', 'size': '4', 'desc': 'Reserved'}, 'Reserved0': {'bit': '3', 'size': '5', 'desc': 'Reserved'}}, 'msr': '0x3A', 'desc': 'Processor Feature Control', 'type': 'msr', 'size': '0x4'}
    + IA32_APIC_BASE  : {'FIELDS': {'x2APICEn': {'bit': '10', 'size': '1', 'desc': 'Enable x2APIC mode'}, 'En': {'bit': '11', 'size': '1', 'desc': 'APIC Global Enable'}, 'BSP': {'bit': '8', 'size': '1', 'desc': 'Bootstrap Processor'}, 'APICBase': {'bit': '12', 'size': '20', 'desc': 'APIC Base'}}, 'msr': '0x1B', 'desc': 'Local APIC Base', 'type': 'msr', 'size': '0x4'}
    + MSR_SMI_COUNT   : {'FIELDS': {'Count': {'bit': '0', 'desc': '', 'size': '64'}}, 'msr': '0x34', 'desc': 'SMI Count', 'type': 'msr', 'size': '0x4'}
[*] loading controls..
    + SmmBiosWriteProtection: {'field': 'SMM_BWP', 'register': 'BC', 'desc': 'SMM BIOS Write Protection'}
    + BiosLockEnable  : {'field': 'BLE', 'register': 'BC', 'desc': 'BIOS Lock Enable'}
    + BiosWriteEnable : {'field': 'BIOSWE', 'register': 'BC', 'desc': 'BIOS Write Enable'}
    + TopSwapStatus   : {'field': 'TSS', 'register': 'BC', 'desc': 'Top Swap Status'}
    + TopSwap         : {'field': 'TS', 'register': 'BUC', 'desc': 'Top Swap'}
    + FlashLockDown   : {'field': 'FLOCKDN', 'register': 'HSFS', 'desc': 'Flash Configuration Lock-Down'}
    + BiosInterfaceLockDown: {'field': 'BILD', 'register': 'GCS', 'desc': 'BIOS Interface Lock-Down'}
    + GlobalSMIEnable : {'field': 'GBL_SMI_EN', 'register': 'SMI_EN', 'desc': 'Global SMI Enable'}
    + GPIOSMIEnable   : {'field': 'GPIO_UNLOCK_SMI_EN', 'register': 'SMI_EN', 'desc': 'GPIO Config SMI Enable'}
    + SMILock         : {'field': 'SMI_LOCK', 'register': 'GEN_PMCON_1', 'desc': 'SMI Global Configuration Lock'}
    + TCOSMIEnable    : {'field': 'TCO_EN', 'register': 'SMI_EN', 'desc': 'TCO SMI Enable'}
    + TCOSMILock      : {'field': 'TCO_LOCK', 'register': 'TCO1_CNT', 'desc': 'TCO SMI Lock'}
    + SMRAMDLock      : {'field': 'D_LCK', 'register': 'PCI0.0.0_SMRAMC', 'desc': 'SMRAM D_LCK'}
    + TSEGBaseLock    : {'field': 'LOCK', 'register': 'PCI0.0.0_TSEGMB', 'desc': 'TSEG Base Lock'}
    + TSEGLimitLock   : {'field': 'LOCK', 'register': 'PCI0.0.0_BGSM', 'desc': 'TSEG Limit Lock'}
    + Ia32FeatureControlLock: {'field': 'LOCK', 'register': 'IA32_FEATURE_CONTROL', 'desc': 'Lock IA32 Feature Control'}
[*] looking for platform config in '/Users/sabri/Desktop/chipsec-master/chipsec/cfg/iommu.xml'..
[*] loading common platform config from '/Users/sabri/Desktop/chipsec-master/chipsec/cfg/iommu.xml'..
[*] loading integrated devices/controllers..
[*] loading MMIO BARs..
[*] loading I/O BARs..
[*] loading memory ranges..
[*] loading configuration registers..
    + VTBAR_VER       : {'bar': 'VTBAR', 'offset': '0x00', 'FIELDS': {'MAX': {'bit': '4', 'size': '4', 'desc': 'Major Version Number'}, 'MIN': {'bit': '0', 'size': '4', 'desc': 'Minor Version Number'}}, 'desc': 'Version', 'type': 'mmio', 'size': '4'}
    + VTBAR_CAP       : {'bar': 'VTBAR', 'offset': '0x08', 'FIELDS': {'R4': {'bit': '60', 'size': '4', 'desc': 'Reserved'}, 'FL1GP': {'bit': '56', 'size': '1', 'desc': 'First Level 1-GB Page Support'}, 'ZLR': {'bit': '22', 'size': '1', 'desc': 'Zero Length Read'}, 'DRD': {'bit': '55', 'size': '1', 'desc': 'Read Draining'}, 'RWBF': {'bit': '4', 'size': '1', 'desc': 'Required Write-Buffer Flushing'}, 'R2': {'bit': '38', 'size': '1', 'desc': 'Reserved'}, 'ND': {'bit': '0', 'size': '2', 'desc': 'Number of Domains Supported'}, 'SLLPS': {'bit': '34', 'size': '4', 'desc': 'Second Level Large Page Support'}, 'MGAW': {'bit': '16', 'size': '6', 'desc': 'Maximum Guest Address Width'}, 'PHMR': {'bit': '6', 'size': '1', 'desc': 'Protected High-Memory Region'}, 'PI': {'bit': '59', 'size': '1', 'desc': 'Posted Interrupts Support'}, 'AFL': {'bit': '3', 'size': '1', 'desc': 'Advanced Fault Logging'}, 'R0': {'bit': '13', 'size': '3', 'desc': 'Reserved'}, 'R1': {'bit': '23', 'size': '1', 'desc': 'Reserved'}, 'CM': {'bit': '7', 'size': '1', 'desc': 'Caching Mode'}, 'R3': {'bit': '57', 'size': '2', 'desc': 'Reserved'}, 'FRO': {'bit': '24', 'size': '10', 'desc': 'Fault-Recording Registrer Offset'}, 'NFR': {'bit': '40', 'size': '8', 'desc': 'Number of Fault-Recording Registers'}, 'DWD': {'bit': '54', 'size': '1', 'desc': 'Write Draining'}, 'PSI': {'bit': '39', 'size': '1', 'desc': 'Page Selective Invalidation'}, 'MAMV': {'bit': '48', 'size': '6', 'desc': 'Maximum Address Mask Value'}, 'SAGAW': {'bit': '8', 'size': '5', 'desc': 'Supported Adjusted Guest Address Width'}, 'PLMR': {'bit': '5', 'size': '1', 'desc': 'Protected Low-Memory Region'}}, 'desc': 'Capability', 'type': 'mmio', 'size': '4'}
    + VTBAR_ECAP      : {'bar': 'VTBAR', 'offset': '0x10', 'FIELDS': {'NWFS': {'bit': '33', 'size': '1', 'desc': 'No Write Flag Support'}, 'ERS': {'bit': '30', 'size': '1', 'desc': 'Execute Request Support'}, 'NEST': {'bit': '26', 'size': '1', 'desc': 'Nested Translation Support'}, 'MHMV': {'bit': '20', 'size': '4', 'desc': 'Maximum Handle Mask Value'}, 'DT': {'bit': '2', 'size': '1', 'desc': 'Device-TLB Support'}, 'EIM': {'bit': '4', 'size': '1', 'desc': 'Extended Interrupt Mode'}, 'DIS': {'bit': '27', 'size': '1', 'desc': 'Deferred Invalidate Support'}, 'PT': {'bit': '6', 'size': '1', 'desc': 'Pass Through'}, 'ECS': {'bit': '24', 'size': '1', 'desc': 'Extended Context Support'}, 'QI': {'bit': '1', 'size': '1', 'desc': 'Queued Invalidation Support'}, 'PRS': {'bit': '29', 'size': '1', 'desc': 'Page Request Support'}, 'C': {'bit': '0', 'size': '1', 'desc': 'Page-walk Coherency'}, 'R0': {'bit': '5', 'size': '1', 'desc': 'Reserved'}, 'R1': {'bit': '18', 'size': '2', 'desc': 'Reserved'}, 'R2': {'bit': '32', 'size': '1', 'desc': 'Reserved'}, 'R3': {'bit': '40', 'size': '24', 'desc': 'Reserved'}, 'MTS': {'bit': '25', 'size': '1', 'desc': 'Memory Type Support'}, 'IR': {'bit': '3', 'size': '1', 'desc': 'Interrupt Remapping Support'}, 'SRS': {'bit': '31', 'size': '1', 'desc': 'Supervisor Request Support'}, 'EAFS': {'bit': '34', 'size': '1', 'desc': 'Extended Accessed Flag Support'}, 'IRO': {'bit': '8', 'size': '10', 'desc': 'IOTLB Register Offset'}, 'PASID': {'bit': '28', 'size': '1', 'desc': 'Process Address Space ID Support'}, 'SC': {'bit': '7', 'size': '1', 'desc': 'Snoop Control'}, 'PSS': {'bit': '35', 'size': '5', 'desc': 'PASID Size Supported'}}, 'desc': 'Global Command', 'type': 'mmio', 'size': '8'}
    + VTBAR_GCMD      : {'bar': 'VTBAR', 'offset': '0x18', 'FIELDS': {'SIRTP': {'bit': '24', 'size': '1', 'desc': 'Set Interrupt Remap Table Pointer'}, 'SRTP': {'bit': '30', 'size': '1', 'desc': 'Set Root Table Pointer'}, 'CFI': {'bit': '23', 'size': '1', 'desc': 'Compatibility Format Interrupt'}, 'QIE': {'bit': '26', 'size': '1', 'desc': 'Queued Invalidation Enable'}, 'Rsvd': {'bit': '0', 'size': '23', 'desc': 'Reserved'}, 'EAFL': {'bit': '28', 'size': '1', 'desc': 'Enable Advanced Fault Logging'}, 'WBF': {'bit': '27', 'size': '1', 'desc': 'Write Buffer Flush'}, 'SFL': {'bit': '29', 'size': '1', 'desc': 'Set Fault Log'}, 'TE': {'bit': '31', 'size': '1', 'desc': 'Translation Enable'}, 'IRE': {'bit': '25', 'size': '1', 'desc': 'Interrupt Remapping Enable'}}, 'desc': 'Global Command', 'type': 'mmio', 'size': '4'}
    + VTBAR_GSTS      : {'bar': 'VTBAR', 'offset': '0x1C', 'FIELDS': {'IRTPS': {'bit': '24', 'size': '1', 'desc': 'Interrupt Remap Table Pointer Status'}, 'TES': {'bit': '31', 'size': '1', 'desc': 'Translation Enable Status'}, 'FLS': {'bit': '29', 'size': '1', 'desc': 'Fault Log Status'}, 'Rsvd': {'bit': '0', 'size': '23', 'desc': 'Reserved'}, 'IRES': {'bit': '25', 'size': '1', 'desc': 'Interrupt Remapping Enable Status'}, 'WBFS': {'bit': '27', 'size': '1', 'desc': 'Write Buffer Flush Status'}, 'RTPS': {'bit': '30', 'size': '1', 'desc': 'Root Table Pointer Status'}, 'QIES': {'bit': '26', 'size': '1', 'desc': 'Queued Invalidation Enable Status'}, 'CFIS': {'bit': '23', 'size': '1', 'desc': 'Compatibility Format Interrupt Status'}, 'AFLS': {'bit': '28', 'size': '1', 'desc': 'Advanced Fault Logging Status'}}, 'desc': 'Global Status', 'type': 'mmio', 'size': '4'}
    + VTBAR_RTADDR    : {'bar': 'VTBAR', 'offset': '0x20', 'FIELDS': {'RTT': {'bit': '11', 'size': '1', 'desc': 'Root Table Type'}, 'R': {'bit': '0', 'size': '11', 'desc': 'Reserved'}, 'RTA': {'bit': '12', 'size': '52', 'desc': 'Root Table Address'}}, 'desc': 'Root-Entry Table Address', 'type': 'mmio', 'size': '8'}
    + VTBAR_CCMD      : {'bar': 'VTBAR', 'offset': '0x28', 'FIELDS': {'DID': {'bit': '0', 'size': '16', 'desc': 'Device ID'}, 'CAIG': {'bit': '59', 'size': '2', 'desc': 'Context Actual Invalidation Granularity'}, 'ICC': {'bit': '63', 'size': '1', 'desc': 'Invalidate Context-Cache'}, 'R': {'bit': '34', 'size': '25', 'desc': 'Reserved'}, 'CIRG': {'bit': '61', 'size': '2', 'desc': 'Context Invalidation Request Granularity'}, 'SID': {'bit': '16', 'size': '16', 'desc': 'Source ID'}, 'FM': {'bit': '32', 'size': '2', 'desc': 'Function Mask'}}, 'desc': 'Context Command', 'type': 'mmio', 'size': '8'}
    + VTBAR_IVA       : {'bar': 'VTBAR', 'offset': '0x0', 'desc': 'Invalidate Address', 'type': 'mmio', 'size': '8'}
    + VTBAR_IOTLB     : {'bar': 'VTBAR', 'offset': '0x8', 'desc': 'IOTLB Invalidate', 'type': 'mmio', 'size': '8'}
    + VTBAR_FSTS      : {'bar': 'VTBAR', 'offset': '0x34', 'FIELDS': {'AFO': {'bit': '2', 'size': '1', 'desc': 'Advanced Fault Overflow'}, 'PPF': {'bit': '1', 'size': '1', 'desc': 'Primary Pending Fault'}, 'PRO': {'bit': '7', 'size': '1', 'desc': 'Page Request Overflow'}, 'ITE': {'bit': '6', 'size': '1', 'desc': 'Invalidation Time-out Error'}, 'ICE': {'bit': '5', 'size': '1', 'desc': 'Invalidation Completion Error'}, 'PFO': {'bit': '0', 'size': '1', 'desc': 'Primary Fault Overflow'}, 'IQE': {'bit': '4', 'size': '1', 'desc': 'Invalidation Queue Error'}, 'APF': {'bit': '3', 'size': '1', 'desc': 'Advanced Pending Fault'}, 'FRI': {'bit': '8', 'size': '7', 'desc': 'Fault Record Index'}}, 'desc': 'Fault Status', 'type': 'mmio', 'size': '4'}
    + VTBAR_FECTL     : {'bar': 'VTBAR', 'offset': '0x38', 'FIELDS': {'IP': {'bit': '30', 'size': '1', 'desc': 'Interrupt Pending'}, 'R': {'bit': '0', 'size': '30', 'desc': 'Reserved'}, 'IM': {'bit': '31', 'size': '1', 'desc': 'Interrupt Mask'}}, 'desc': 'Fault Event Control', 'type': 'mmio', 'size': '4'}
    + VTBAR_FEDATA    : {'bar': 'VTBAR', 'offset': '0x3C', 'FIELDS': {'IMD': {'bit': '0', 'size': '16', 'desc': 'Interrupt Message Data'}, 'EIMD': {'bit': '16', 'size': '16', 'desc': 'Extended Interrupt Message Data'}}, 'desc': 'Fault Event Data', 'type': 'mmio', 'size': '4'}
    + VTBAR_FEADDR    : {'bar': 'VTBAR', 'offset': '0x40', 'FIELDS': {'R': {'bit': '0', 'size': '2', 'desc': 'Reserved'}, 'MA': {'bit': '2', 'size': '30', 'desc': 'Message Address'}}, 'desc': 'Fault Event Address', 'type': 'mmio', 'size': '4'}
    + VTBAR_FEUADDR   : {'bar': 'VTBAR', 'offset': '0x44', 'FIELDS': {'MUA': {'bit': '0', 'size': '32', 'desc': 'Message Upper Address'}}, 'desc': 'Fault Event Upper Address', 'type': 'mmio', 'size': '4'}
    + VTBAR_FRCDL     : {'bar': 'VTBAR', 'offset': '0x0', 'desc': 'Fault Recording (Low)', 'type': 'mmio', 'size': '8'}
    + VTBAR_FRCDH     : {'bar': 'VTBAR', 'offset': '0x8', 'desc': 'Fault Recording (High)', 'type': 'mmio', 'size': '8'}
    + VTBAR_AFL       : {'bar': 'VTBAR', 'offset': '0x58', 'FIELDS': {'FLA': {'bit': '0', 'size': '52', 'desc': 'Fault Log Address'}, 'FLS': {'bit': '9', 'size': '3', 'desc': 'Fault Log Size'}, 'R': {'bit': '0', 'size': '9', 'desc': 'Reserved'}}, 'desc': 'Advanced Fault Log', 'type': 'mmio', 'size': '8'}
    + VTBAR_PMEN      : {'bar': 'VTBAR', 'offset': '0x64', 'FIELDS': {'EPM': {'bit': '31', 'size': '1', 'desc': 'Enable Protected Memory'}, 'PRS': {'bit': '0', 'size': '1', 'desc': 'Protected Region Status'}}, 'desc': 'Protected Memory Enable', 'type': 'mmio', 'size': '4'}
    + VTBAR_PLMBASE   : {'bar': 'VTBAR', 'offset': '0x68', 'FIELDS': {'PLMB': {'bit': '12', 'size': '20', 'desc': 'Protected Low-Memory Base'}}, 'desc': 'Protected Memory Low Base', 'type': 'mmio', 'size': '4'}
    + VTBAR_PLMLIMIT  : {'bar': 'VTBAR', 'offset': '0x6C', 'FIELDS': {'PLML': {'bit': '12', 'size': '20', 'desc': 'Protected Low-Memory Limit'}}, 'desc': 'Protected Memory Low Limit', 'type': 'mmio', 'size': '4'}
    + VTBAR_PHMBASE   : {'bar': 'VTBAR', 'offset': '0x70', 'FIELDS': {'PHMB': {'bit': '12', 'size': '52', 'desc': 'Protected High-Memory Base'}}, 'desc': 'Protected Memory High Base', 'type': 'mmio', 'size': '8'}
    + VTBAR_PHMLIMIT  : {'bar': 'VTBAR', 'offset': '0x78', 'FIELDS': {'PHML': {'bit': '12', 'size': '52', 'desc': 'Protected High-Memory Limit'}}, 'desc': 'Protected Memory High Limit', 'type': 'mmio', 'size': '8'}
    + VTBAR_IQH       : {'bar': 'VTBAR', 'offset': '0x80', 'FIELDS': {'QH': {'bit': '4', 'size': '15', 'desc': 'Queue Head'}}, 'desc': 'Invalidation Queue Head', 'type': 'mmio', 'size': '8'}
    + VTBAR_IQT       : {'bar': 'VTBAR', 'offset': '0x88', 'FIELDS': {'QT': {'bit': '4', 'size': '15', 'desc': 'Queue Tail'}}, 'desc': 'Invalidation Queue Tail', 'type': 'mmio', 'size': '8'}
    + VTBAR_IQA       : {'bar': 'VTBAR', 'offset': '0x90', 'FIELDS': {'QS': {'bit': '0', 'size': '3', 'desc': 'Queue Size'}, 'IQA': {'bit': '12', 'size': '52', 'desc': 'Invalidation Queue Base Address'}}, 'desc': 'Invalidation Queue Address', 'type': 'mmio', 'size': '8'}
    + VTBAR_ICS       : {'bar': 'VTBAR', 'offset': '0x9C', 'FIELDS': {'IWC': {'bit': '0', 'size': '1', 'desc': 'Invalidation Wait Descriptor Complete'}}, 'desc': 'Invalidation Completion Status', 'type': 'mmio', 'size': '4'}
    + VTBAR_IECTL     : {'bar': 'VTBAR', 'offset': '0xA0', 'desc': 'Invalidation Event Control', 'type': 'mmio', 'size': '4'}
    + VTBAR_IEDATA    : {'bar': 'VTBAR', 'offset': '0xA4', 'desc': 'Invalidation Event Data', 'type': 'mmio', 'size': '4'}
    + VTBAR_IEADDR    : {'bar': 'VTBAR', 'offset': '0xA8', 'desc': 'Invalidation Event Address', 'type': 'mmio', 'size': '4'}
    + VTBAR_IEUADDR   : {'bar': 'VTBAR', 'offset': '0xAC', 'desc': 'Invalidation Event Address', 'type': 'mmio', 'size': '4'}
    + VTBAR_IRTA      : {'bar': 'VTBAR', 'offset': '0xB8', 'FIELDS': {'IRTA': {'bit': '12', 'size': '52', 'desc': 'Interrupt Remapping Table Address'}, 'S': {'bit': '0', 'size': '4', 'desc': 'Size'}, 'EIME': {'bit': '11', 'size': '1', 'desc': 'Extended Interrupt Mode Enable'}}, 'desc': 'Invalidation Event Upper Address', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_VER    : {'bar': 'GFXVTBAR', 'offset': '0x00', 'FIELDS': {'MAX': {'bit': '4', 'size': '4', 'desc': 'Major Version Number'}, 'MIN': {'bit': '0', 'size': '4', 'desc': 'Minor Version Number'}}, 'desc': 'Version', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_CAP    : {'bar': 'GFXVTBAR', 'offset': '0x08', 'FIELDS': {'R4': {'bit': '60', 'size': '4', 'desc': 'Reserved'}, 'FL1GP': {'bit': '56', 'size': '1', 'desc': 'First Level 1-GB Page Support'}, 'ZLR': {'bit': '22', 'size': '1', 'desc': 'Zero Length Read'}, 'DRD': {'bit': '55', 'size': '1', 'desc': 'Read Draining'}, 'RWBF': {'bit': '4', 'size': '1', 'desc': 'Required Write-Buffer Flushing'}, 'R2': {'bit': '38', 'size': '1', 'desc': 'Reserved'}, 'ND': {'bit': '0', 'size': '2', 'desc': 'Number of Domains Supported'}, 'SLLPS': {'bit': '34', 'size': '4', 'desc': 'Second Level Large Page Support'}, 'MGAW': {'bit': '16', 'size': '6', 'desc': 'Maximum Guest Address Width'}, 'PHMR': {'bit': '6', 'size': '1', 'desc': 'Protected High-Memory Region'}, 'PI': {'bit': '59', 'size': '1', 'desc': 'Posted Interrupts Support'}, 'AFL': {'bit': '3', 'size': '1', 'desc': 'Advanced Fault Logging'}, 'R0': {'bit': '13', 'size': '3', 'desc': 'Reserved'}, 'R1': {'bit': '23', 'size': '1', 'desc': 'Reserved'}, 'CM': {'bit': '7', 'size': '1', 'desc': 'Caching Mode'}, 'R3': {'bit': '57', 'size': '2', 'desc': 'Reserved'}, 'FRO': {'bit': '24', 'size': '10', 'desc': 'Fault-Recording Registrer Offset'}, 'NFR': {'bit': '40', 'size': '8', 'desc': 'Number of Fault-Recording Registers'}, 'DWD': {'bit': '54', 'size': '1', 'desc': 'Write Draining'}, 'PSI': {'bit': '39', 'size': '1', 'desc': 'Page Selective Invalidation'}, 'MAMV': {'bit': '48', 'size': '6', 'desc': 'Maximum Address Mask Value'}, 'SAGAW': {'bit': '8', 'size': '5', 'desc': 'Supported Adjusted Guest Address Width'}, 'PLMR': {'bit': '5', 'size': '1', 'desc': 'Protected Low-Memory Region'}}, 'desc': 'Capability', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_ECAP   : {'bar': 'GFXVTBAR', 'offset': '0x10', 'FIELDS': {'NWFS': {'bit': '33', 'size': '1', 'desc': 'No Write Flag Support'}, 'ERS': {'bit': '30', 'size': '1', 'desc': 'Execute Request Support'}, 'NEST': {'bit': '26', 'size': '1', 'desc': 'Nested Translation Support'}, 'MHMV': {'bit': '20', 'size': '4', 'desc': 'Maximum Handle Mask Value'}, 'DT': {'bit': '2', 'size': '1', 'desc': 'Device-TLB Support'}, 'EIM': {'bit': '4', 'size': '1', 'desc': 'Extended Interrupt Mode'}, 'DIS': {'bit': '27', 'size': '1', 'desc': 'Deferred Invalidate Support'}, 'PT': {'bit': '6', 'size': '1', 'desc': 'Pass Through'}, 'ECS': {'bit': '24', 'size': '1', 'desc': 'Extended Context Support'}, 'QI': {'bit': '1', 'size': '1', 'desc': 'Queued Invalidation Support'}, 'PRS': {'bit': '29', 'size': '1', 'desc': 'Page Request Support'}, 'C': {'bit': '0', 'size': '1', 'desc': 'Page-walk Coherency'}, 'R0': {'bit': '5', 'size': '1', 'desc': 'Reserved'}, 'R1': {'bit': '18', 'size': '2', 'desc': 'Reserved'}, 'R2': {'bit': '32', 'size': '1', 'desc': 'Reserved'}, 'R3': {'bit': '40', 'size': '24', 'desc': 'Reserved'}, 'MTS': {'bit': '25', 'size': '1', 'desc': 'Memory Type Support'}, 'IR': {'bit': '3', 'size': '1', 'desc': 'Interrupt Remapping Support'}, 'SRS': {'bit': '31', 'size': '1', 'desc': 'Supervisor Request Support'}, 'EAFS': {'bit': '34', 'size': '1', 'desc': 'Extended Accessed Flag Support'}, 'IRO': {'bit': '8', 'size': '10', 'desc': 'IOTLB Register Offset'}, 'PASID': {'bit': '28', 'size': '1', 'desc': 'Process Address Space ID Support'}, 'SC': {'bit': '7', 'size': '1', 'desc': 'Snoop Control'}, 'PSS': {'bit': '35', 'size': '5', 'desc': 'PASID Size Supported'}}, 'desc': 'Global Command', 'type': 'mmio', 'size': '8'}
    + GFXVTBAR_GCMD   : {'bar': 'GFXVTBAR', 'offset': '0x18', 'FIELDS': {'SIRTP': {'bit': '24', 'size': '1', 'desc': 'Set Interrupt Remap Table Pointer'}, 'SRTP': {'bit': '30', 'size': '1', 'desc': 'Set Root Table Pointer'}, 'CFI': {'bit': '23', 'size': '1', 'desc': 'Compatibility Format Interrupt'}, 'QIE': {'bit': '26', 'size': '1', 'desc': 'Queued Invalidation Enable'}, 'Rsvd': {'bit': '0', 'size': '23', 'desc': 'Reserved'}, 'EAFL': {'bit': '28', 'size': '1', 'desc': 'Enable Advanced Fault Logging'}, 'WBF': {'bit': '27', 'size': '1', 'desc': 'Write Buffer Flush'}, 'SFL': {'bit': '29', 'size': '1', 'desc': 'Set Fault Log'}, 'TE': {'bit': '31', 'size': '1', 'desc': 'Translation Enable'}, 'IRE': {'bit': '25', 'size': '1', 'desc': 'Interrupt Remapping Enable'}}, 'desc': 'Global Command', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_GSTS   : {'bar': 'GFXVTBAR', 'offset': '0x1C', 'FIELDS': {'IRTPS': {'bit': '24', 'size': '1', 'desc': 'Interrupt Remap Table Pointer Status'}, 'TES': {'bit': '31', 'size': '1', 'desc': 'Translation Enable Status'}, 'FLS': {'bit': '29', 'size': '1', 'desc': 'Fault Log Status'}, 'Rsvd': {'bit': '0', 'size': '23', 'desc': 'Reserved'}, 'IRES': {'bit': '25', 'size': '1', 'desc': 'Interrupt Remapping Enable Status'}, 'WBFS': {'bit': '27', 'size': '1', 'desc': 'Write Buffer Flush Status'}, 'RTPS': {'bit': '30', 'size': '1', 'desc': 'Root Table Pointer Status'}, 'QIES': {'bit': '26', 'size': '1', 'desc': 'Queued Invalidation Enable Status'}, 'CFIS': {'bit': '23', 'size': '1', 'desc': 'Compatibility Format Interrupt Status'}, 'AFLS': {'bit': '28', 'size': '1', 'desc': 'Advanced Fault Logging Status'}}, 'desc': 'Global Status', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_RTADDR : {'bar': 'GFXVTBAR', 'offset': '0x20', 'FIELDS': {'RTT': {'bit': '11', 'size': '1', 'desc': 'Root Table Type'}, 'R': {'bit': '0', 'size': '11', 'desc': 'Reserved'}, 'RTA': {'bit': '12', 'size': '52', 'desc': 'Root Table Address'}}, 'desc': 'Root-Entry Table Address', 'type': 'mmio', 'size': '8'}
    + GFXVTBAR_CCMD   : {'bar': 'GFXVTBAR', 'offset': '0x28', 'FIELDS': {'DID': {'bit': '0', 'size': '16', 'desc': 'Device ID'}, 'CAIG': {'bit': '59', 'size': '2', 'desc': 'Context Actual Invalidation Granularity'}, 'ICC': {'bit': '63', 'size': '1', 'desc': 'Invalidate Context-Cache'}, 'R': {'bit': '34', 'size': '25', 'desc': 'Reserved'}, 'CIRG': {'bit': '61', 'size': '2', 'desc': 'Context Invalidation Request Granularity'}, 'SID': {'bit': '16', 'size': '16', 'desc': 'Source ID'}, 'FM': {'bit': '32', 'size': '2', 'desc': 'Function Mask'}}, 'desc': 'Context Command', 'type': 'mmio', 'size': '8'}
    + GFXVTBAR_IVA    : {'bar': 'GFXVTBAR', 'offset': '0x0', 'desc': 'Invalidate Address', 'type': 'mmio', 'size': '8'}
    + GFXVTBAR_IOTLB  : {'bar': 'GFXVTBAR', 'offset': '0x8', 'desc': 'IOTLB Invalidate', 'type': 'mmio', 'size': '8'}
    + GFXVTBAR_FSTS   : {'bar': 'GFXVTBAR', 'offset': '0x34', 'FIELDS': {'AFO': {'bit': '2', 'size': '1', 'desc': 'Advanced Fault Overflow'}, 'PPF': {'bit': '1', 'size': '1', 'desc': 'Primary Pending Fault'}, 'PRO': {'bit': '7', 'size': '1', 'desc': 'Page Request Overflow'}, 'ITE': {'bit': '6', 'size': '1', 'desc': 'Invalidation Time-out Error'}, 'ICE': {'bit': '5', 'size': '1', 'desc': 'Invalidation Completion Error'}, 'PFO': {'bit': '0', 'size': '1', 'desc': 'Primary Fault Overflow'}, 'IQE': {'bit': '4', 'size': '1', 'desc': 'Invalidation Queue Error'}, 'APF': {'bit': '3', 'size': '1', 'desc': 'Advanced Pending Fault'}, 'FRI': {'bit': '8', 'size': '7', 'desc': 'Fault Record Index'}}, 'desc': 'Fault Status', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_FECTL  : {'bar': 'GFXVTBAR', 'offset': '0x38', 'FIELDS': {'IP': {'bit': '30', 'size': '1', 'desc': 'Interrupt Pending'}, 'R': {'bit': '0', 'size': '30', 'desc': 'Reserved'}, 'IM': {'bit': '31', 'size': '1', 'desc': 'Interrupt Mask'}}, 'desc': 'Fault Event Control', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_FEDATA : {'bar': 'GFXVTBAR', 'offset': '0x3C', 'FIELDS': {'IMD': {'bit': '0', 'size': '16', 'desc': 'Interrupt Message Data'}, 'EIMD': {'bit': '16', 'size': '16', 'desc': 'Extended Interrupt Message Data'}}, 'desc': 'Fault Event Data', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_FEADDR : {'bar': 'GFXVTBAR', 'offset': '0x40', 'FIELDS': {'R': {'bit': '0', 'size': '2', 'desc': 'Reserved'}, 'MA': {'bit': '2', 'size': '30', 'desc': 'Message Address'}}, 'desc': 'Fault Event Address', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_FEUADDR: {'bar': 'GFXVTBAR', 'offset': '0x44', 'FIELDS': {'MUA': {'bit': '0', 'size': '32', 'desc': 'Message Upper Address'}}, 'desc': 'Fault Event Upper Address', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_FRCDL  : {'bar': 'GFXVTBAR', 'offset': '0x0', 'desc': 'Fault Recording (Low)', 'type': 'mmio', 'size': '8'}
    + GFXVTBAR_FRCDH  : {'bar': 'GFXVTBAR', 'offset': '0x8', 'desc': 'Fault Recording (High)', 'type': 'mmio', 'size': '8'}
    + GFXVTBAR_AFL    : {'bar': 'GFXVTBAR', 'offset': '0x58', 'FIELDS': {'FLA': {'bit': '0', 'size': '52', 'desc': 'Fault Log Address'}, 'FLS': {'bit': '9', 'size': '3', 'desc': 'Fault Log Size'}, 'R': {'bit': '0', 'size': '9', 'desc': 'Reserved'}}, 'desc': 'Advanced Fault Log', 'type': 'mmio', 'size': '8'}
    + GFXVTBAR_PMEN   : {'bar': 'GFXVTBAR', 'offset': '0x64', 'FIELDS': {'EPM': {'bit': '31', 'size': '1', 'desc': 'Enable Protected Memory'}, 'PRS': {'bit': '0', 'size': '1', 'desc': 'Protected Region Status'}}, 'desc': 'Protected Memory Enable', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_PLMBASE: {'bar': 'GFXVTBAR', 'offset': '0x68', 'FIELDS': {'PLMB': {'bit': '12', 'size': '20', 'desc': 'Protected Low-Memory Base'}}, 'desc': 'Protected Memory Low Base', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_PLMLIMIT: {'bar': 'GFXVTBAR', 'offset': '0x6C', 'FIELDS': {'PLML': {'bit': '12', 'size': '20', 'desc': 'Protected Low-Memory Limit'}}, 'desc': 'Protected Memory Low Limit', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_PHMBASE: {'bar': 'GFXVTBAR', 'offset': '0x70', 'FIELDS': {'PHMB': {'bit': '12', 'size': '52', 'desc': 'Protected High-Memory Base'}}, 'desc': 'Protected Memory High Base', 'type': 'mmio', 'size': '8'}
    + GFXVTBAR_PHMLIMIT: {'bar': 'GFXVTBAR', 'offset': '0x78', 'FIELDS': {'PHML': {'bit': '12', 'size': '52', 'desc': 'Protected High-Memory Limit'}}, 'desc': 'Protected Memory High Limit', 'type': 'mmio', 'size': '8'}
    + GFXVTBAR_IQH    : {'bar': 'GFXVTBAR', 'offset': '0x80', 'FIELDS': {'QH': {'bit': '4', 'size': '15', 'desc': 'Queue Head'}}, 'desc': 'Invalidation Queue Head', 'type': 'mmio', 'size': '8'}
    + GFXVTBAR_IQT    : {'bar': 'GFXVTBAR', 'offset': '0x88', 'FIELDS': {'QT': {'bit': '4', 'size': '15', 'desc': 'Queue Tail'}}, 'desc': 'Invalidation Queue Tail', 'type': 'mmio', 'size': '8'}
    + GFXVTBAR_IQA    : {'bar': 'GFXVTBAR', 'offset': '0x90', 'FIELDS': {'QS': {'bit': '0', 'size': '3', 'desc': 'Queue Size'}, 'IQA': {'bit': '12', 'size': '52', 'desc': 'Invalidation Queue Base Address'}}, 'desc': 'Invalidation Queue Address', 'type': 'mmio', 'size': '8'}
    + GFXVTBAR_ICS    : {'bar': 'GFXVTBAR', 'offset': '0x9C', 'FIELDS': {'IWC': {'bit': '0', 'size': '1', 'desc': 'Invalidation Wait Descriptor Complete'}}, 'desc': 'Invalidation Completion Status', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_IECTL  : {'bar': 'GFXVTBAR', 'offset': '0xA0', 'desc': 'Invalidation Event Control', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_IEDATA : {'bar': 'GFXVTBAR', 'offset': '0xA4', 'desc': 'Invalidation Event Data', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_IEADDR : {'bar': 'GFXVTBAR', 'offset': '0xA8', 'desc': 'Invalidation Event Address', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_IEUADDR: {'bar': 'GFXVTBAR', 'offset': '0xAC', 'desc': 'Invalidation Event Address', 'type': 'mmio', 'size': '4'}
    + GFXVTBAR_IRTA   : {'bar': 'GFXVTBAR', 'offset': '0xB8', 'FIELDS': {'IRTA': {'bit': '12', 'size': '52', 'desc': 'Interrupt Remapping Table Address'}, 'S': {'bit': '0', 'size': '4', 'desc': 'Size'}, 'EIME': {'bit': '11', 'size': '1', 'desc': 'Extended Interrupt Mode Enable'}}, 'desc': 'Invalidation Event Upper Address', 'type': 'mmio', 'size': '4'}
[*] loading controls..
[*] looking for platform config in '/Users/sabri/Desktop/chipsec-master/chipsec/cfg/template.xml'..
ERROR: Unsupported Platform: VID = 0x8086, DID = 0x1610
ERROR: Platform is not supported (Unsupported Platform: VID = 0x8086, DID = 0x1610).
WARNING: Platform dependent functionality is likely to be incorrect
[CHIPSEC] OS      : Darwin 16.4.0 Darwin Kernel Version 16.4.0: Thu Dec 22 22:53:21 PST 2016; root:xnu-3789.41.3~3/RELEASE_X86_64 x86_64
[CHIPSEC] Platform: UnknownPlatform
[CHIPSEC]      VID: 8086
[CHIPSEC]      DID: 1610
 
[*] Running from /Users/sabri/Desktop/chipsec-master
[*] loading common modules from "./chipsec/modules/common" ..
[*] Path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common
[+] loaded chipsec.modules.common.bios_kbrd_buffer
[+] loaded chipsec.modules.common.bios_smi
[+] loaded chipsec.modules.common.bios_ts
[+] loaded chipsec.modules.common.bios_wp
[+] loaded chipsec.modules.common.ia32cfg
[+] loaded chipsec.modules.common.rtclock
[+] loaded chipsec.modules.common.smm
[+] loaded chipsec.modules.common.smrr
[+] loaded chipsec.modules.common.spi_desc
[+] loaded chipsec.modules.common.spi_fdopss
[+] loaded chipsec.modules.common.spi_lock
[+] loaded chipsec.modules.common.secureboot.variables
[+] loaded chipsec.modules.common.uefi.access_uefispec
[+] loaded chipsec.modules.common.uefi.s3bootscript
[*] No platform specific modules to load
[*] loading modules from "./chipsec/modules" ..
[*] Path: /Users/sabri/Desktop/chipsec-master/chipsec/modules
[+] loaded chipsec.modules.memconfig
[+] loaded chipsec.modules.remap
[+] loaded chipsec.modules.smm_dma
[*] running loaded modules ..

[*] running module: chipsec.modules.common.bios_kbrd_buffer
[+] imported: chipsec.modules.common.bios_kbrd_buffer
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common/bios_kbrd_buffer.pyc
[x][ =======================================================================
[x][ Module: Pre-boot Passwords in the BIOS Keyboard Buffer
[x][ =======================================================================
[mem] 0x000000000000041A
[mem] dword at PA = 0x000000000000041A: 0x00000000
[mem] 0x000000000000041C
[mem] dword at PA = 0x000000000000041C: 0x00000000
[*] Keyboard buffer head pointer = 0x0 (at 0x41A), tail pointer = 0x0 (at 0x41C)
[mem] 0x000000000000041E
[*] Keyboard buffer contents (at 0x41E):
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |                 
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |                 
[*] Checking contents of the keyboard buffer..

[+] PASSED: Keyboard buffer looks empty. Pre-boot passwords don't seem to be exposed

[*] running module: chipsec.modules.common.bios_smi
[+] imported: chipsec.modules.common.bios_smi
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common/bios_smi.pyc
[x][ =======================================================================
[x][ Module: SMI Events Configuration
[x][ =======================================================================
[pci] reading B/D/F: 0/31/0, offset: 0xDC, value: 0x08
[-] SMM BIOS region write protection has not been enabled (SMM_BWP is not used)

[*] Checking SMI enables..
[iobar] read ABASE + 0x30 (4)
[pci] reading B/D/F: 0/31/0, offset: 0x40, value: 0x00001801
[iobar] ABASE: 0x1800 (size = 0x80)
[-] Traceback (most recent call last):
  File "chipsec_main.py", line 227, in run_module
    result = modx.run( module_argv )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/module.py", line 76, in run
    result = self.mod_obj.run(module_argv)
  File "/Users/sabri/Desktop/chipsec-master/chipsec/modules/common/bios_smi.py", line 126, in run
    return self.check_SMI_locks()
  File "/Users/sabri/Desktop/chipsec-master/chipsec/modules/common/bios_smi.py", line 73, in check_SMI_locks
    tco_en     = self.cs.get_control( 'TCOSMIEnable' )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/chipset.py", line 676, in get_control
    reg_data = self.read_register(reg)
  File "/Users/sabri/Desktop/chipsec-master/chipsec/chipset.py", line 539, in read_register
    reg_value = self.iobar.read_IO_BAR_reg( reg['bar'], int(reg['offset'],16), int(reg['size'],16) )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/hal/iobar.py", line 109, in read_IO_BAR_reg
    value = self.cs.io._read_port( io_port, size )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/hal/io.py", line 61, in _read_port
    value = self.helper.read_io_port( io_port, size )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/helper/oshelper.py", line 263, in read_io_port
    return self.helper.read_io_port( io_port, size )
TypeError: read_io_port() takes exactly 1 argument (3 given)

ERROR: Exception occurred during chipsec.modules.common.bios_smi.run(): 'read_io_port() takes exactly 1 argument (3 given)'
[-] Traceback (most recent call last):
  File "chipsec_main.py", line 359, in run_loaded_modules
    result = self.run_module( modx, modx_argv )
  File "chipsec_main.py", line 233, in run_module
    raise msg
TypeError: read_io_port() takes exactly 1 argument (3 given)


[*] running module: chipsec.modules.common.bios_ts
[+] imported: chipsec.modules.common.bios_ts
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common/bios_ts.pyc
[x][ =======================================================================
[x][ Module: BIOS Interface Lock (including Top Swap Mode)
[x][ =======================================================================
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] RCBA: 0x00000000FED1C000 (size = 0x4000)
[mmio] 0xFED1C000 + 0x00003410 = 0x00000C21
[*] BiosInterfaceLockDown (BILD) control = 1
[pci] reading B/D/F: 0/31/0, offset: 0xDC, value: 0x08
[*] BIOS Top Swap mode is disabled (TSS = 0)
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] RCBA: 0x00000000FED1C000 (size = 0x4000)
[mmio] 0xFED1C000 + 0x00003414 = 0x00000020
[*] RTC TopSwap control (TS) = 0
[+] PASSED: BIOS Interface is locked (including Top Swap Mode)

[*] running module: chipsec.modules.common.bios_wp
[+] imported: chipsec.modules.common.bios_wp
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common/bios_wp.pyc
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[spi] SPI MMIO base: 0x00000000FED1F800 (assuming below 4GB)
[spi] Reading SPI flash controller registers definitions:
      HSFC   offset = 0x0006
      HSFS   offset = 0x0004
      FADDR  offset = 0x0008
      FDATA0 offset = 0x0010
[x][ =======================================================================
[x][ Module: BIOS Region Write Protection
[x][ =======================================================================
[pci] reading B/D/F: 0/31/0, offset: 0xDC, value: 0x08
[*] BC = 0x08 << BIOS Control (b:d.f 00:31.0 + 0xDC)
    [00] BIOSWE           = 0 << BIOS Write Enable 
    [01] BLE              = 0 << BIOS Lock Enable 
    [02] SRC              = 2 << SPI Read Configuration 
    [04] TSS              = 0 << Top Swap Status 
    [05] SMM_BWP          = 0 << SMM BIOS Write Protection 
[pci] reading B/D/F: 0/31/0, offset: 0xDC, value: 0x08
[pci] reading B/D/F: 0/31/0, offset: 0xDC, value: 0x08
[-] BIOS region write protection is disabled!
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[mmio] 0xFED1F800 + 0x00000058 = 0x07FF018E

[*] BIOS Region: Base = 0x0018E000, Limit = 0x007FFFFF
SPI Protected Ranges
------------------------------------------------------------
PRx (offset) | Value    | Base     | Limit    | WP? | RP?
------------------------------------------------------------
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[mmio] 0xFED1F800 + 0x00000074 = 0x80010000
PR0 (74)     | 80010000 | 00000000 | 00001FFF | 1   | 0 
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[mmio] 0xFED1F800 + 0x00000078 = 0x856F018E
PR1 (78)     | 856F018E | 0018E000 | 0056FFFF | 1   | 0 
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[mmio] 0xFED1F800 + 0x0000007C = 0xFFFF0592
PR2 (7C)     | FFFF0592 | 00592000 | 01FFFFFF | 1   | 0 
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[mmio] 0xFED1F800 + 0x00000080 = 0x00000000
PR3 (80)     | 00000000 | 00000000 | 00000000 | 0   | 0 
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[mmio] 0xFED1F800 + 0x00000084 = 0x00000000
PR4 (84)     | 00000000 | 00000000 | 00000000 | 0   | 0 
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[mmio] 0xFED1F800 + 0x00000074 = 0x80010000
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[mmio] 0xFED1F800 + 0x00000078 = 0x856F018E
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[mmio] 0xFED1F800 + 0x0000007C = 0xFFFF0592
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[mmio] 0xFED1F800 + 0x00000080 = 0x00000000
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[mmio] 0xFED1F800 + 0x00000084 = 0x00000000

[!] SPI protected ranges write-protect parts of BIOS region (other parts of BIOS can be modified)

[!] BIOS should enable all available SMM based write protection mechanisms or configure SPI protected ranges to protect the entire BIOS region
[-] FAILED: BIOS is NOT protected completely

[*] running module: chipsec.modules.common.ia32cfg
[+] imported: chipsec.modules.common.ia32cfg
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common/ia32cfg.pyc
[x][ =======================================================================
[x][ Module: IA32 Feature Control Lock
[x][ =======================================================================
[*] Verifying IA32_Feature_Control MSR is locked on all logical CPUs..
[-] Traceback (most recent call last):
  File "chipsec_main.py", line 227, in run_module
    result = modx.run( module_argv )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/module.py", line 76, in run
    result = self.mod_obj.run(module_argv)
  File "/Users/sabri/Desktop/chipsec-master/chipsec/modules/common/ia32cfg.py", line 65, in run
    return self.check_ia32feature_control()
  File "/Users/sabri/Desktop/chipsec-master/chipsec/modules/common/ia32cfg.py", line 48, in check_ia32feature_control
    for tid in range(self.cs.msr.get_cpu_thread_count()):
  File "/Users/sabri/Desktop/chipsec-master/chipsec/hal/msr.py", line 70, in get_cpu_thread_count
    thread_count = self.helper.get_threads_count()
  File "/Users/sabri/Desktop/chipsec-master/chipsec/helper/oshelper.py", line 416, in get_threads_count
    return self.helper.get_threads_count()
AttributeError: 'OSXHelper' object has no attribute 'get_threads_count'

ERROR: Exception occurred during chipsec.modules.common.ia32cfg.run(): ''OSXHelper' object has no attribute 'get_threads_count''
[-] Traceback (most recent call last):
  File "chipsec_main.py", line 359, in run_loaded_modules
    result = self.run_module( modx, modx_argv )
  File "chipsec_main.py", line 233, in run_module
    raise msg
AttributeError: 'OSXHelper' object has no attribute 'get_threads_count'


[*] running module: chipsec.modules.common.rtclock
[+] imported: chipsec.modules.common.rtclock
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common/rtclock.pyc
Skipping module chipsec.modules.common.rtclock since it is not supported in this platform

[*] running module: chipsec.modules.common.smm
[+] imported: chipsec.modules.common.smm
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common/smm.pyc
[x][ =======================================================================
[x][ Module: Compatible SMM memory (SMRAM) Protection
[x][ =======================================================================
[pci] reading B/D/F: 0/0/0, offset: 0x88, value: 0x1A
[*] PCI0.0.0_SMRAMC = 0x1A << System Management RAM Control (b:d.f 00:00.0 + 0x88)
    [00] C_BASE_SEG       = 2 << SMRAM Base Segment = 010b 
    [03] G_SMRAME         = 1 << SMRAM Enabled 
    [04] D_LCK            = 1 << SMRAM Locked 
    [05] D_CLS            = 0 << SMRAM Closed 
    [06] D_OPEN           = 0 << SMRAM Open 
[*] Compatible SMRAM is enabled
[+] PASSED: Compatible SMRAM is locked down

[*] running module: chipsec.modules.common.smrr
[+] imported: chipsec.modules.common.smrr
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common/smrr.pyc
[x][ =======================================================================
[x][ Module: CPU SMM Cache Poisoning / System Management Range Registers
[x][ =======================================================================
[cpu] CPUID in : EAX=0x00000001, ECX=0x00000000
[-] Traceback (most recent call last):
  File "chipsec_main.py", line 227, in run_module
    result = modx.run( module_argv )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/module.py", line 76, in run
    result = self.mod_obj.run(module_argv)
  File "/Users/sabri/Desktop/chipsec-master/chipsec/modules/common/smrr.py", line 165, in run
    return self.check_SMRR( do_modify )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/modules/common/smrr.py", line 58, in check_SMRR
    if self.cs.cpu.check_SMRR_supported():
  File "/Users/sabri/Desktop/chipsec-master/chipsec/hal/cpu.py", line 200, in check_SMRR_supported
    if self.check_vmm() == VMM_HYPER_V: return False
  File "/Users/sabri/Desktop/chipsec-master/chipsec/hal/cpu.py", line 86, in check_vmm
    (eax, ebx, ecx, edx) = self.cpuid( 0x01, 0 )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/hal/cpu.py", line 79, in cpuid
    (eax, ebx, ecx, edx) = self.helper.cpuid( eax, ecx )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/helper/oshelper.py", line 370, in cpuid
    return self.helper.cpuid( eax, ecx )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/helper/osx/helper.py", line 194, in cpuid
    raise NotImplementedError()
NotImplementedError

ERROR: Exception occurred during chipsec.modules.common.smrr.run(): ''
[-] Traceback (most recent call last):
  File "chipsec_main.py", line 359, in run_loaded_modules
    result = self.run_module( modx, modx_argv )
  File "chipsec_main.py", line 233, in run_module
    raise msg
NotImplementedError


[*] running module: chipsec.modules.common.spi_desc
[+] imported: chipsec.modules.common.spi_desc
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common/spi_desc.pyc
[x][ =======================================================================
[x][ Module: SPI Flash Region Access Control
[x][ =======================================================================
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[mmio] 0xFED1F800 + 0x00000050 = 0x0000FFFF
[*] FRAP = 0x0000FFFF << SPI Flash Regions Access Permissions Register (SPIBAR + 0x50)
    [00] BRRA             = FF << BIOS Region Read Access 
    [08] BRWA             = FF << BIOS Region Write Access 
    [16] BMRAG            = 0 << BIOS Master Read Access Grant 
    [24] BMWAG            = 0 << BIOS Master Write Access Grant 
[*] Software access to SPI flash regions: read = 0xFF, write = 0xFF
[-] Software has write access to SPI flash descriptor

[-] FAILED: SPI flash permissions allow SW to write flash descriptor

[*] running module: chipsec.modules.common.spi_fdopss
[+] imported: chipsec.modules.common.spi_fdopss
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common/spi_fdopss.pyc
[x][ =======================================================================
[x][ Module: SPI Flash Descriptor Security Override Pin-Strap
[x][ =======================================================================
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[mmio] 0xFED1F800 + 0x00000004 = 0x0000F008
[*] HSFS = 0xF008 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4)
    [00] FDONE            = 0 << Flash Cycle Done 
    [01] FCERR            = 0 << Flash Cycle Error 
    [02] AEL              = 0 << Access Error Log 
    [03] BERASE           = 1 << Block/Sector Erase Size 
    [05] SCIP             = 0 << SPI cycle in progress 
    [13] FDOPSS           = 1 << Flash Descriptor Override Pin-Strap Status 
    [14] FDV              = 1 << Flash Descriptor Valid 
    [15] FLOCKDN          = 1 << Flash Configuration Lock-Down 
[+] PASSED: SPI Flash Descriptor Security Override is disabled

[*] running module: chipsec.modules.common.spi_lock
[+] imported: chipsec.modules.common.spi_lock
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common/spi_lock.pyc
[x][ =======================================================================
[x][ Module: SPI Flash Controller Configuration Lock
[x][ =======================================================================
[pci] reading B/D/F: 0/31/0, offset: 0xF0, value: 0xFED1C001
[mmio] SPIBAR: 0x00000000FED1F800 (size = 0x200)
[mmio] 0xFED1F800 + 0x00000004 = 0x0000F008
[*] HSFS = 0xF008 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4)
    [00] FDONE            = 0 << Flash Cycle Done 
    [01] FCERR            = 0 << Flash Cycle Error 
    [02] AEL              = 0 << Access Error Log 
    [03] BERASE           = 1 << Block/Sector Erase Size 
    [05] SCIP             = 0 << SPI cycle in progress 
    [13] FDOPSS           = 1 << Flash Descriptor Override Pin-Strap Status 
    [14] FDV              = 1 << Flash Descriptor Valid 
    [15] FLOCKDN          = 1 << Flash Configuration Lock-Down 
[+] PASSED: SPI Flash Controller configuration is locked

[*] running module: chipsec.modules.common.secureboot.variables
[+] imported: chipsec.modules.common.secureboot.variables
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common/secureboot/variables.pyc
[-] Traceback (most recent call last):
  File "chipsec_main.py", line 227, in run_module
    result = modx.run( module_argv )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/module.py", line 75, in run
    if self.mod_obj.is_supported() :
  File "/Users/sabri/Desktop/chipsec-master/chipsec/modules/common/secureboot/variables.py", line 55, in is_supported
    supported = self.cs.helper.EFI_supported()
  File "/Users/sabri/Desktop/chipsec-master/chipsec/helper/oshelper.py", line 323, in EFI_supported
    return self.helper.EFI_supported()
AttributeError: 'OSXHelper' object has no attribute 'EFI_supported'

ERROR: Exception occurred during chipsec.modules.common.secureboot.variables.run(): ''OSXHelper' object has no attribute 'EFI_supported''
[-] Traceback (most recent call last):
  File "chipsec_main.py", line 359, in run_loaded_modules
    result = self.run_module( modx, modx_argv )
  File "chipsec_main.py", line 233, in run_module
    raise msg
AttributeError: 'OSXHelper' object has no attribute 'EFI_supported'


[*] running module: chipsec.modules.common.uefi.access_uefispec
[+] imported: chipsec.modules.common.uefi.access_uefispec
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common/uefi/access_uefispec.pyc
[-] Traceback (most recent call last):
  File "chipsec_main.py", line 227, in run_module
    result = modx.run( module_argv )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/module.py", line 75, in run
    if self.mod_obj.is_supported() :
  File "/Users/sabri/Desktop/chipsec-master/chipsec/modules/common/uefi/access_uefispec.py", line 90, in is_supported
    supported = self.cs.helper.EFI_supported()
  File "/Users/sabri/Desktop/chipsec-master/chipsec/helper/oshelper.py", line 323, in EFI_supported
    return self.helper.EFI_supported()
AttributeError: 'OSXHelper' object has no attribute 'EFI_supported'

ERROR: Exception occurred during chipsec.modules.common.uefi.access_uefispec.run(): ''OSXHelper' object has no attribute 'EFI_supported''
[-] Traceback (most recent call last):
  File "chipsec_main.py", line 359, in run_loaded_modules
    result = self.run_module( modx, modx_argv )
  File "chipsec_main.py", line 233, in run_module
    raise msg
AttributeError: 'OSXHelper' object has no attribute 'EFI_supported'


[*] running module: chipsec.modules.common.uefi.s3bootscript
[+] imported: chipsec.modules.common.uefi.s3bootscript
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/common/uefi/s3bootscript.pyc
[-] Traceback (most recent call last):
  File "chipsec_main.py", line 227, in run_module
    result = modx.run( module_argv )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/module.py", line 75, in run
    if self.mod_obj.is_supported() :
  File "/Users/sabri/Desktop/chipsec-master/chipsec/modules/common/uefi/s3bootscript.py", line 76, in is_supported
    supported = self.cs.helper.EFI_supported()
  File "/Users/sabri/Desktop/chipsec-master/chipsec/helper/oshelper.py", line 323, in EFI_supported
    return self.helper.EFI_supported()
AttributeError: 'OSXHelper' object has no attribute 'EFI_supported'

ERROR: Exception occurred during chipsec.modules.common.uefi.s3bootscript.run(): ''OSXHelper' object has no attribute 'EFI_supported''
[-] Traceback (most recent call last):
  File "chipsec_main.py", line 359, in run_loaded_modules
    result = self.run_module( modx, modx_argv )
  File "chipsec_main.py", line 233, in run_module
    raise msg
AttributeError: 'OSXHelper' object has no attribute 'EFI_supported'


[*] running module: chipsec.modules.memconfig
[+] imported: chipsec.modules.memconfig
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/memconfig.pyc
Skipping module chipsec.modules.memconfig since it is not supported in this platform

[*] running module: chipsec.modules.remap
[+] imported: chipsec.modules.remap
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/remap.pyc
Skipping module chipsec.modules.remap since it is not supported in this platform

[*] running module: chipsec.modules.smm_dma
[+] imported: chipsec.modules.smm_dma
[*] Module path: /Users/sabri/Desktop/chipsec-master/chipsec/modules/smm_dma.pyc
[x][ =======================================================================
[x][ Module: SMM TSEG Range Configuration Check
[x][ =======================================================================
[pci] reading B/D/F: 0/0/0, offset: 0xB8, value: 0x89000001
[pci] reading B/D/F: 0/0/0, offset: 0xB4, value: 0x89800001
[*] TSEG      : 0x0000000089000000 - 0x00000000897FFFFF (size = 0x00800000)
[cpu] CPUID in : EAX=0x00000001, ECX=0x00000000
[-] Traceback (most recent call last):
  File "chipsec_main.py", line 227, in run_module
    result = modx.run( module_argv )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/module.py", line 76, in run
    result = self.mod_obj.run(module_argv)
  File "/Users/sabri/Desktop/chipsec-master/chipsec/modules/smm_dma.py", line 98, in run
    self.res = self.check_tseg_config()
  File "/Users/sabri/Desktop/chipsec-master/chipsec/modules/smm_dma.py", line 65, in check_tseg_config
    if (self.cs.cpu.check_SMRR_supported()):
  File "/Users/sabri/Desktop/chipsec-master/chipsec/hal/cpu.py", line 200, in check_SMRR_supported
    if self.check_vmm() == VMM_HYPER_V: return False
  File "/Users/sabri/Desktop/chipsec-master/chipsec/hal/cpu.py", line 86, in check_vmm
    (eax, ebx, ecx, edx) = self.cpuid( 0x01, 0 )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/hal/cpu.py", line 79, in cpuid
    (eax, ebx, ecx, edx) = self.helper.cpuid( eax, ecx )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/helper/oshelper.py", line 370, in cpuid
    return self.helper.cpuid( eax, ecx )
  File "/Users/sabri/Desktop/chipsec-master/chipsec/helper/osx/helper.py", line 194, in cpuid
    raise NotImplementedError()
NotImplementedError

ERROR: Exception occurred during chipsec.modules.smm_dma.run(): ''
[-] Traceback (most recent call last):
  File "chipsec_main.py", line 359, in run_loaded_modules
    result = self.run_module( modx, modx_argv )
  File "chipsec_main.py", line 233, in run_module
    raise msg
NotImplementedError


[CHIPSEC] ***************************  SUMMARY  ***************************
[CHIPSEC] Time elapsed          0.036
[CHIPSEC] Modules total         17
[CHIPSEC] Modules failed to run 7:
ERROR: chipsec.modules.common.bios_smi
ERROR: chipsec.modules.common.ia32cfg
ERROR: chipsec.modules.common.smrr
ERROR: chipsec.modules.common.secureboot.variables
ERROR: chipsec.modules.common.uefi.access_uefispec
ERROR: chipsec.modules.common.uefi.s3bootscript
ERROR: chipsec.modules.smm_dma
[CHIPSEC] Modules passed        5:
[+] PASSED: chipsec.modules.common.bios_kbrd_buffer
[+] PASSED: chipsec.modules.common.bios_ts
[+] PASSED: chipsec.modules.common.smm
[+] PASSED: chipsec.modules.common.spi_fdopss
[+] PASSED: chipsec.modules.common.spi_lock
[CHIPSEC] Modules failed        2:
[-] FAILED: chipsec.modules.common.bios_wp
[-] FAILED: chipsec.modules.common.spi_desc
[CHIPSEC] Modules with warnings 0:
[CHIPSEC] Modules skipped 3:
[*] SKIPPED: chipsec.modules.common.rtclock
[*] SKIPPED: chipsec.modules.memconfig
[*] SKIPPED: chipsec.modules.remap
[CHIPSEC] Modules with Exceptions 7:
ERROR: chipsec.modules.common.bios_smi
ERROR: chipsec.modules.common.ia32cfg
ERROR: chipsec.modules.common.smrr
ERROR: chipsec.modules.common.secureboot.variables
ERROR: chipsec.modules.common.uefi.access_uefispec
ERROR: chipsec.modules.common.uefi.s3bootscript
ERROR: chipsec.modules.smm_dma
[CHIPSEC] *****************************************************************
[helper] OSX Helper stopped/unloaded
[helper] OSX Helper deleted

@ghost
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ghost commented Mar 14, 2017 •
edited by ghost

Here is also the version related to the EFI/SMC:

  Boot ROM Version:	IM162.0207.B07
  SMC Version (system):	2.32f20

I believe they are up to date since I am using the latest version of macOS.

Edit:

https://support.apple.com/en-us/HT201518

It looks like my iMac is not even on the Apple EFI/SMC firmwares page.

Edit:

A benchmark of the same Mac as me from Feb. 2017 is showing the same EFI version: https://browser.primatelabs.com/v4/compute/455770 so I think it's "up to date".

@c7zero
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c7zero commented Mar 14, 2017

ERROR results in modules are due to certain functions not implemented in macOS helper yet (cpuid and EFI_supported). Will be adding these functions... For now, I'd recommend booting off of USB drive with Linux and chipsec.

@c7zero
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c7zero commented Mar 19, 2017

Due to PR #184 modules which raised exceptions will be now skipped when run on macOS. I'll open a new issue to implement missing functionality these modules rely on so that they can run on macOS.

@c7zero
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c7zero commented Mar 19, 2017

Issue #149 tracks this

@ghost
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ghost commented Mar 19, 2017

Thanks you but what about the FAILED then? I'm unsure using Linux will fix this but I could try when I'll have the time.

@c7zero
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c7zero commented Mar 19, 2017

FAILED modules will also be FAILED when you run under Linux. The two modules returned FAILED because they didn't find specific protections they were looking for. common.bios_wp module failed because your Mac doesn't use SMM based protection of EFI firmware. Instead, it apears to be using PR1-PR2 protected ranges (see the second part of bios_wp log) but they don't cover entire EFI region. common.spi_desc module failed because the system doesn't seem to be restricting access to flash descriptor region via permissions defined in the descriptor itself. Based on the log, your Mac appears to be "soft" protection (PR0 range) to protect flash descriptor. This may be ok but without further analysis I cannot tell if it's a sufficient protection or the firmware can be compromised/corrupted.

@ghost
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ghost commented Mar 20, 2017 •
edited by ghost

Thanks you but considering that it is probably the same results on every Mac I think your script might need some adjustments.

@c7zero
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c7zero commented Mar 21, 2017

I have a Mac with different results.
Each module checks for individual protection (or a vulnerability) present/missing on a system and fails if cannot find it. However, the system may be using some alternative protection mechanism which is either checked by some other module, in which case other module will pass, or CHIPSEC doesn't known about this protection, in which case you'd need to do some manual checking. For example, a system may be using write-protection of a SPI device on a device itself instead of using chipset based mechanisms. The sure way to test for all these is attempt to write to SPI chip and see what happens. You can easily do that with CHIPSEC (chipsec_util spi write) but you are risking to brick your system so we cannot have an automatically running module doing this.
Thanks for suggestion! It makes sense to add notes whenever possible about alternative ways to protect the firmware. Closing the issue.

@c7zero c7zero closed this as completed Mar 21, 2017
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