-
Notifications
You must be signed in to change notification settings - Fork 4
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Deploying to gh-pages from @ b35b2ba 🚀
- Loading branch information
Showing
4 changed files
with
131 additions
and
131 deletions.
There are no files selected for viewing
72 changes: 36 additions & 36 deletions
72
chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2021-09-09.log
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,44 +1,44 @@ | ||
| ===-------------------------------------------------------------------------=== | ||
| ... Execution time report ... | ||
| ===-------------------------------------------------------------------------=== | ||
| Total Execution Time: 16.4704 seconds | ||
| Total Execution Time: 16.5776 seconds | ||
|
|
||
| ----User Time---- ----Wall Time---- ----Name---- | ||
| 3.9369 ( 18.6%) 3.9369 ( 23.9%) FIR Parser | ||
| 10.0877 ( 47.8%) 6.8746 ( 41.7%) 'firrtl.circuit' Pipeline | ||
| 1.9159 ( 9.1%) 0.9592 ( 5.8%) 'firrtl.module' Pipeline | ||
| 1.7394 ( 8.2%) 0.8834 ( 5.4%) CSE | ||
| 0.0011 ( 0.0%) 0.0006 ( 0.0%) (A) DominanceInfo | ||
| 0.1718 ( 0.8%) 0.0983 ( 0.6%) LowerCHIRRTL | ||
| 0.1100 ( 0.5%) 0.1100 ( 0.7%) InferWidths | ||
| 0.7243 ( 3.4%) 0.7243 ( 4.4%) InferResets | ||
| 0.0387 ( 0.2%) 0.0387 ( 0.2%) (A) circt::firrtl::InstanceGraph | ||
| 0.6971 ( 3.3%) 0.6971 ( 4.2%) LowerFIRRTLTypes | ||
| 3.0370 ( 14.4%) 1.5227 ( 9.2%) 'firrtl.module' Pipeline | ||
| 1.1912 ( 5.6%) 0.6011 ( 3.6%) ExpandWhens | ||
| 1.8412 ( 8.7%) 0.9216 ( 5.6%) Canonicalizer | ||
| 0.5006 ( 2.4%) 0.5006 ( 3.0%) Inliner | ||
| 1.6180 ( 7.7%) 1.6180 ( 9.8%) IMConstProp | ||
| 0.0440 ( 0.2%) 0.0440 ( 0.3%) (A) circt::firrtl::InstanceGraph | ||
| 0.0003 ( 0.0%) 0.0003 ( 0.0%) BlackBoxReader | ||
| 1.4706 ( 7.0%) 0.7370 ( 4.5%) 'firrtl.module' Pipeline | ||
| 1.4680 ( 7.0%) 0.7359 ( 4.5%) Canonicalizer | ||
| 0.9194 ( 4.4%) 0.9194 ( 5.6%) LowerFIRRTLToHW | ||
| 0.2140 ( 1.0%) 0.2140 ( 1.3%) HWMemSimImpl | ||
| 2.4293 ( 11.5%) 1.2155 ( 7.4%) 'hw.module' Pipeline | ||
| 0.0578 ( 0.3%) 0.0297 ( 0.2%) HWCleanup | ||
| 0.8188 ( 3.9%) 0.4175 ( 2.5%) CSE | ||
| 0.0014 ( 0.0%) 0.0007 ( 0.0%) (A) DominanceInfo | ||
| 1.5324 ( 7.3%) 0.7727 ( 4.7%) Canonicalizer | ||
| 0.0110 ( 0.1%) 0.0056 ( 0.0%) HWLegalizeModules | ||
| 0.3712 ( 1.8%) 0.3712 ( 2.3%) HWLegalizeNames | ||
| 0.4350 ( 2.1%) 0.2180 ( 1.3%) 'hw.module' Pipeline | ||
| 0.4309 ( 2.0%) 0.2162 ( 1.3%) PrettifyVerilog | ||
| 2.7090 ( 12.8%) 2.7090 ( 16.4%) ExportVerilog emission | ||
| 0.0069 ( 0.0%) 0.0069 ( 0.0%) Rest | ||
| 21.1159 (100.0%) 16.4704 (100.0%) Total | ||
| 3.6791 ( 18.1%) 3.6791 ( 22.2%) FIR Parser | ||
| 8.0242 ( 39.6%) 5.5629 ( 33.6%) 'firrtl.circuit' Pipeline | ||
| 1.5571 ( 7.7%) 0.7796 ( 4.7%) 'firrtl.module' Pipeline | ||
| 1.4033 ( 6.9%) 0.7032 ( 4.2%) CSE | ||
| 0.0010 ( 0.0%) 0.0005 ( 0.0%) (A) DominanceInfo | ||
| 0.1497 ( 0.7%) 0.0756 ( 0.5%) LowerCHIRRTL | ||
| 0.1457 ( 0.7%) 0.1457 ( 0.9%) InferWidths | ||
| 0.6295 ( 3.1%) 0.6295 ( 3.8%) InferResets | ||
| 0.0495 ( 0.2%) 0.0495 ( 0.3%) (A) circt::firrtl::InstanceGraph | ||
| 0.5129 ( 2.5%) 0.5129 ( 3.1%) LowerFIRRTLTypes | ||
| 2.2453 ( 11.1%) 1.1252 ( 6.8%) 'firrtl.module' Pipeline | ||
| 0.8598 ( 4.2%) 0.4441 ( 2.7%) ExpandWhens | ||
| 1.3813 ( 6.8%) 0.7024 ( 4.2%) Canonicalizer | ||
| 0.3859 ( 1.9%) 0.3859 ( 2.3%) Inliner | ||
| 1.4160 ( 7.0%) 1.4160 ( 8.5%) IMConstProp | ||
| 0.0460 ( 0.2%) 0.0460 ( 0.3%) (A) circt::firrtl::InstanceGraph | ||
| 0.0002 ( 0.0%) 0.0002 ( 0.0%) BlackBoxReader | ||
| 1.1209 ( 5.5%) 0.5622 ( 3.4%) 'firrtl.module' Pipeline | ||
| 1.1185 ( 5.5%) 0.5611 ( 3.4%) Canonicalizer | ||
| 0.9138 ( 4.5%) 0.9138 ( 5.5%) LowerFIRRTLToHW | ||
| 0.2030 ( 1.0%) 0.2030 ( 1.2%) HWMemSimImpl | ||
| 2.1087 ( 10.4%) 1.0545 ( 6.4%) 'hw.module' Pipeline | ||
| 0.0597 ( 0.3%) 0.0311 ( 0.2%) HWCleanup | ||
| 0.7029 ( 3.5%) 0.3608 ( 2.2%) CSE | ||
| 0.0012 ( 0.0%) 0.0007 ( 0.0%) (A) DominanceInfo | ||
| 1.3262 ( 6.5%) 0.6735 ( 4.1%) Canonicalizer | ||
| 0.0110 ( 0.1%) 0.0062 ( 0.0%) HWLegalizeModules | ||
| 0.3747 ( 1.8%) 0.3747 ( 2.3%) HWLegalizeNames | ||
| 0.3864 ( 1.9%) 0.1935 ( 1.2%) 'hw.module' Pipeline | ||
| 0.3830 ( 1.9%) 0.1919 ( 1.2%) PrettifyVerilog | ||
| 4.5858 ( 22.6%) 4.5858 ( 27.7%) ExportVerilog emission | ||
| 0.0062 ( 0.0%) 0.0062 ( 0.0%) Rest | ||
| 20.2861 (100.0%) 16.5776 (100.0%) Total | ||
|
|
||
| { | ||
| totalTime: 16.511, | ||
| maxMemory: 864460800 | ||
| totalTime: 16.613, | ||
| maxMemory: 865320960 | ||
| } |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,44 +1,44 @@ | ||
| ===-------------------------------------------------------------------------=== | ||
| ... Execution time report ... | ||
| ===-------------------------------------------------------------------------=== | ||
| Total Execution Time: 1.2018 seconds | ||
| Total Execution Time: 1.0995 seconds | ||
|
|
||
| ----User Time---- ----Wall Time---- ----Name---- | ||
| 0.2788 ( 18.3%) 0.2788 ( 23.2%) FIR Parser | ||
| 1.0075 ( 66.2%) 0.6879 ( 57.2%) 'firrtl.circuit' Pipeline | ||
| 0.1306 ( 8.6%) 0.0719 ( 6.0%) 'firrtl.module' Pipeline | ||
| 0.1152 ( 7.6%) 0.0633 ( 5.3%) CSE | ||
| 0.2382 ( 16.6%) 0.2382 ( 21.7%) FIR Parser | ||
| 0.9742 ( 67.9%) 0.6400 ( 58.2%) 'firrtl.circuit' Pipeline | ||
| 0.1674 ( 11.7%) 0.1018 ( 9.3%) 'firrtl.module' Pipeline | ||
| 0.1538 ( 10.7%) 0.0958 ( 8.7%) CSE | ||
| 0.0000 ( 0.0%) 0.0000 ( 0.0%) (A) DominanceInfo | ||
| 0.0153 ( 1.0%) 0.0086 ( 0.7%) LowerCHIRRTL | ||
| 0.0123 ( 0.8%) 0.0123 ( 1.0%) InferWidths | ||
| 0.0505 ( 3.3%) 0.0505 ( 4.2%) InferResets | ||
| 0.0018 ( 0.1%) 0.0018 ( 0.2%) (A) circt::firrtl::InstanceGraph | ||
| 0.1272 ( 8.4%) 0.1272 ( 10.6%) LowerFIRRTLTypes | ||
| 0.5463 ( 35.9%) 0.2853 ( 23.7%) 'firrtl.module' Pipeline | ||
| 0.0967 ( 6.4%) 0.0488 ( 4.1%) ExpandWhens | ||
| 0.4496 ( 29.6%) 0.2365 ( 19.7%) Canonicalizer | ||
| 0.0195 ( 1.3%) 0.0195 ( 1.6%) Inliner | ||
| 0.0245 ( 1.6%) 0.0245 ( 2.0%) IMConstProp | ||
| 0.0135 ( 0.9%) 0.0075 ( 0.7%) LowerCHIRRTL | ||
| 0.0131 ( 0.9%) 0.0131 ( 1.2%) InferWidths | ||
| 0.0447 ( 3.1%) 0.0447 ( 4.1%) InferResets | ||
| 0.0014 ( 0.1%) 0.0014 ( 0.1%) (A) circt::firrtl::InstanceGraph | ||
| 0.0886 ( 6.2%) 0.0886 ( 8.1%) LowerFIRRTLTypes | ||
| 0.4907 ( 34.2%) 0.2582 ( 23.5%) 'firrtl.module' Pipeline | ||
| 0.0792 ( 5.5%) 0.0435 ( 4.0%) ExpandWhens | ||
| 0.4115 ( 28.7%) 0.2147 ( 19.5%) Canonicalizer | ||
| 0.0193 ( 1.3%) 0.0193 ( 1.8%) Inliner | ||
| 0.0252 ( 1.8%) 0.0252 ( 2.3%) IMConstProp | ||
| 0.0004 ( 0.0%) 0.0004 ( 0.0%) (A) circt::firrtl::InstanceGraph | ||
| 0.0000 ( 0.0%) 0.0000 ( 0.0%) BlackBoxReader | ||
| 0.0963 ( 6.3%) 0.0963 ( 8.0%) 'firrtl.module' Pipeline | ||
| 0.0963 ( 6.3%) 0.0963 ( 8.0%) Canonicalizer | ||
| 0.0798 ( 5.2%) 0.0798 ( 6.6%) LowerFIRRTLToHW | ||
| 0.0887 ( 6.2%) 0.0887 ( 8.1%) 'firrtl.module' Pipeline | ||
| 0.0887 ( 6.2%) 0.0887 ( 8.1%) Canonicalizer | ||
| 0.0739 ( 5.2%) 0.0739 ( 6.7%) LowerFIRRTLToHW | ||
| 0.0000 ( 0.0%) 0.0000 ( 0.0%) HWMemSimImpl | ||
| 0.0853 ( 5.6%) 0.0853 ( 7.1%) 'hw.module' Pipeline | ||
| 0.0009 ( 0.1%) 0.0009 ( 0.1%) HWCleanup | ||
| 0.0255 ( 1.7%) 0.0255 ( 2.1%) CSE | ||
| 0.0810 ( 5.6%) 0.0810 ( 7.4%) 'hw.module' Pipeline | ||
| 0.0010 ( 0.1%) 0.0010 ( 0.1%) HWCleanup | ||
| 0.0242 ( 1.7%) 0.0242 ( 2.2%) CSE | ||
| 0.0000 ( 0.0%) 0.0000 ( 0.0%) (A) DominanceInfo | ||
| 0.0581 ( 3.8%) 0.0581 ( 4.8%) Canonicalizer | ||
| 0.0549 ( 3.8%) 0.0549 ( 5.0%) Canonicalizer | ||
| 0.0008 ( 0.1%) 0.0008 ( 0.1%) HWLegalizeModules | ||
| 0.0050 ( 0.3%) 0.0050 ( 0.4%) HWLegalizeNames | ||
| 0.0147 ( 1.0%) 0.0147 ( 1.2%) 'hw.module' Pipeline | ||
| 0.0147 ( 1.0%) 0.0147 ( 1.2%) PrettifyVerilog | ||
| 0.0493 ( 3.2%) 0.0493 ( 4.1%) ExportVerilog emission | ||
| 0.0009 ( 0.1%) 0.0009 ( 0.1%) Rest | ||
| 1.5215 (100.0%) 1.2018 (100.0%) Total | ||
| 0.0050 ( 0.4%) 0.0050 ( 0.5%) HWLegalizeNames | ||
| 0.0136 ( 1.0%) 0.0136 ( 1.2%) 'hw.module' Pipeline | ||
| 0.0136 ( 1.0%) 0.0136 ( 1.2%) PrettifyVerilog | ||
| 0.0469 ( 3.3%) 0.0469 ( 4.3%) ExportVerilog emission | ||
| 0.0008 ( 0.1%) 0.0008 ( 0.1%) Rest | ||
| 1.4338 (100.0%) 1.0995 (100.0%) Total | ||
|
|
||
| { | ||
| totalTime: 1.211, | ||
| maxMemory: 68759552 | ||
| totalTime: 1.108, | ||
| maxMemory: 68632576 | ||
| } |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,44 +1,44 @@ | ||
| ===-------------------------------------------------------------------------=== | ||
| ... Execution time report ... | ||
| ===-------------------------------------------------------------------------=== | ||
| Total Execution Time: 31.8366 seconds | ||
| Total Execution Time: 30.1359 seconds | ||
|
|
||
| ----Wall Time---- ----Name---- | ||
| 3.8954 ( 12.2%) FIR Parser | ||
| 15.1724 ( 47.7%) 'firrtl.circuit' Pipeline | ||
| 1.4090 ( 4.4%) 'firrtl.module' Pipeline | ||
| 1.2895 ( 4.1%) CSE | ||
| 3.5505 ( 11.8%) FIR Parser | ||
| 14.2213 ( 47.2%) 'firrtl.circuit' Pipeline | ||
| 1.3156 ( 4.4%) 'firrtl.module' Pipeline | ||
| 1.2007 ( 4.0%) CSE | ||
| 0.0000 ( 0.0%) (A) DominanceInfo | ||
| 0.1195 ( 0.4%) LowerCHIRRTL | ||
| 0.0987 ( 0.3%) InferWidths | ||
| 0.7251 ( 2.3%) InferResets | ||
| 0.0217 ( 0.1%) (A) circt::firrtl::InstanceGraph | ||
| 0.7577 ( 2.4%) LowerFIRRTLTypes | ||
| 6.4839 ( 20.4%) 'firrtl.module' Pipeline | ||
| 0.9648 ( 3.0%) ExpandWhens | ||
| 5.5191 ( 17.3%) Canonicalizer | ||
| 0.4155 ( 1.3%) Inliner | ||
| 1.1580 ( 3.6%) IMConstProp | ||
| 0.0364 ( 0.1%) (A) circt::firrtl::InstanceGraph | ||
| 0.1148 ( 0.4%) LowerCHIRRTL | ||
| 0.1099 ( 0.4%) InferWidths | ||
| 0.6803 ( 2.3%) InferResets | ||
| 0.0253 ( 0.1%) (A) circt::firrtl::InstanceGraph | ||
| 0.6609 ( 2.2%) LowerFIRRTLTypes | ||
| 5.9777 ( 19.8%) 'firrtl.module' Pipeline | ||
| 0.8252 ( 2.7%) ExpandWhens | ||
| 5.1524 ( 17.1%) Canonicalizer | ||
| 0.3861 ( 1.3%) Inliner | ||
| 1.0828 ( 3.6%) IMConstProp | ||
| 0.0359 ( 0.1%) (A) circt::firrtl::InstanceGraph | ||
| 0.0000 ( 0.0%) BlackBoxReader | ||
| 4.1243 ( 13.0%) 'firrtl.module' Pipeline | ||
| 4.1243 ( 13.0%) Canonicalizer | ||
| 2.4581 ( 7.7%) LowerFIRRTLToHW | ||
| 4.0079 ( 13.3%) 'firrtl.module' Pipeline | ||
| 4.0079 ( 13.3%) Canonicalizer | ||
| 2.2983 ( 7.6%) LowerFIRRTLToHW | ||
| 0.0000 ( 0.0%) HWMemSimImpl | ||
| 7.2332 ( 22.7%) 'hw.module' Pipeline | ||
| 0.0877 ( 0.3%) HWCleanup | ||
| 1.0892 ( 3.4%) CSE | ||
| 7.0487 ( 23.4%) 'hw.module' Pipeline | ||
| 0.0892 ( 0.3%) HWCleanup | ||
| 1.0130 ( 3.4%) CSE | ||
| 0.0000 ( 0.0%) (A) DominanceInfo | ||
| 5.9794 ( 18.8%) Canonicalizer | ||
| 0.0769 ( 0.2%) HWLegalizeModules | ||
| 0.3081 ( 1.0%) HWLegalizeNames | ||
| 0.8580 ( 2.7%) 'hw.module' Pipeline | ||
| 0.8580 ( 2.7%) PrettifyVerilog | ||
| 1.9095 ( 6.0%) ExportVerilog emission | ||
| 5.8683 ( 19.5%) Canonicalizer | ||
| 0.0782 ( 0.3%) HWLegalizeModules | ||
| 0.3216 ( 1.1%) HWLegalizeNames | ||
| 0.8497 ( 2.8%) 'hw.module' Pipeline | ||
| 0.8497 ( 2.8%) PrettifyVerilog | ||
| 1.8440 ( 6.1%) ExportVerilog emission | ||
| 0.0017 ( 0.0%) Rest | ||
| 31.8366 (100.0%) Total | ||
| 30.1359 (100.0%) Total | ||
|
|
||
| { | ||
| totalTime: 31.863, | ||
| maxMemory: 596111360 | ||
| totalTime: 30.162, | ||
| maxMemory: 592625664 | ||
| } |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,44 +1,44 @@ | ||
| ===-------------------------------------------------------------------------=== | ||
| ... Execution time report ... | ||
| ===-------------------------------------------------------------------------=== | ||
| Total Execution Time: 32.2818 seconds | ||
| Total Execution Time: 29.5479 seconds | ||
|
|
||
| ----User Time---- ----Wall Time---- ----Name---- | ||
| 9.7694 ( 22.2%) 9.7694 ( 30.3%) FIR Parser | ||
| 23.1901 ( 52.8%) 14.1827 ( 43.9%) 'firrtl.circuit' Pipeline | ||
| 2.9237 ( 6.7%) 1.6224 ( 5.0%) 'firrtl.module' Pipeline | ||
| 2.6249 ( 6.0%) 1.4600 ( 4.5%) CSE | ||
| 9.1851 ( 22.6%) 9.1851 ( 31.1%) FIR Parser | ||
| 22.5412 ( 55.4%) 13.4999 ( 45.7%) 'firrtl.circuit' Pipeline | ||
| 2.7388 ( 6.7%) 1.5301 ( 5.2%) 'firrtl.module' Pipeline | ||
| 2.4618 ( 6.0%) 1.3779 ( 4.7%) CSE | ||
| 0.0000 ( 0.0%) 0.0000 ( 0.0%) (A) DominanceInfo | ||
| 0.2988 ( 0.7%) 0.1624 ( 0.5%) LowerCHIRRTL | ||
| 0.2610 ( 0.6%) 0.2610 ( 0.8%) InferWidths | ||
| 1.2926 ( 2.9%) 1.2926 ( 4.0%) InferResets | ||
| 0.0661 ( 0.2%) 0.0661 ( 0.2%) (A) circt::firrtl::InstanceGraph | ||
| 1.7089 ( 3.9%) 1.7089 ( 5.3%) LowerFIRRTLTypes | ||
| 10.5770 ( 24.1%) 5.8476 ( 18.1%) 'firrtl.module' Pipeline | ||
| 3.6934 ( 8.4%) 2.0465 ( 6.3%) ExpandWhens | ||
| 6.8836 ( 15.7%) 3.8011 ( 11.8%) Canonicalizer | ||
| 0.3053 ( 0.7%) 0.3053 ( 0.9%) Inliner | ||
| 1.0812 ( 2.5%) 1.0812 ( 3.3%) IMConstProp | ||
| 0.0384 ( 0.1%) 0.0384 ( 0.1%) (A) circt::firrtl::InstanceGraph | ||
| 0.2769 ( 0.7%) 0.1521 ( 0.5%) LowerCHIRRTL | ||
| 0.2971 ( 0.7%) 0.2971 ( 1.0%) InferWidths | ||
| 1.2623 ( 3.1%) 1.2623 ( 4.3%) InferResets | ||
| 0.0838 ( 0.2%) 0.0838 ( 0.3%) (A) circt::firrtl::InstanceGraph | ||
| 1.5108 ( 3.7%) 1.5108 ( 5.1%) LowerFIRRTLTypes | ||
| 9.8435 ( 24.2%) 5.4932 ( 18.6%) 'firrtl.module' Pipeline | ||
| 3.2838 ( 8.1%) 1.8119 ( 6.1%) ExpandWhens | ||
| 6.5596 ( 16.1%) 3.6813 ( 12.5%) Canonicalizer | ||
| 0.3164 ( 0.8%) 0.3164 ( 1.1%) Inliner | ||
| 1.0614 ( 2.6%) 1.0614 ( 3.6%) IMConstProp | ||
| 0.0430 ( 0.1%) 0.0430 ( 0.1%) (A) circt::firrtl::InstanceGraph | ||
| 0.0000 ( 0.0%) 0.0000 ( 0.0%) BlackBoxReader | ||
| 3.5916 ( 8.2%) 2.0542 ( 6.4%) 'firrtl.module' Pipeline | ||
| 3.5915 ( 8.2%) 2.0542 ( 6.4%) Canonicalizer | ||
| 1.6004 ( 3.6%) 1.6004 ( 5.0%) LowerFIRRTLToHW | ||
| 1.0255 ( 2.3%) 1.0255 ( 3.2%) HWMemSimImpl | ||
| 3.9832 ( 9.1%) 2.0717 ( 6.4%) 'hw.module' Pipeline | ||
| 0.1562 ( 0.4%) 0.0842 ( 0.3%) HWCleanup | ||
| 1.6677 ( 3.8%) 0.9140 ( 2.8%) CSE | ||
| 0.0082 ( 0.0%) 0.0046 ( 0.0%) (A) DominanceInfo | ||
| 2.0869 ( 4.7%) 1.0494 ( 3.3%) Canonicalizer | ||
| 0.0119 ( 0.0%) 0.0064 ( 0.0%) HWLegalizeModules | ||
| 0.9771 ( 2.2%) 0.9771 ( 3.0%) HWLegalizeNames | ||
| 1.3673 ( 3.1%) 0.7594 ( 2.4%) 'hw.module' Pipeline | ||
| 1.3465 ( 3.1%) 0.7492 ( 2.3%) PrettifyVerilog | ||
| 1.8689 ( 4.3%) 1.8689 ( 5.8%) ExportVerilog emission | ||
| 0.0027 ( 0.0%) 0.0027 ( 0.0%) Rest | ||
| 43.9601 (100.0%) 32.2818 (100.0%) Total | ||
| 3.5708 ( 8.8%) 2.0180 ( 6.8%) 'firrtl.module' Pipeline | ||
| 3.5708 ( 8.8%) 2.0180 ( 6.8%) Canonicalizer | ||
| 1.4097 ( 3.5%) 1.4097 ( 4.8%) LowerFIRRTLToHW | ||
| 0.8137 ( 2.0%) 0.8137 ( 2.8%) HWMemSimImpl | ||
| 3.2081 ( 7.9%) 1.6296 ( 5.5%) 'hw.module' Pipeline | ||
| 0.1396 ( 0.3%) 0.0757 ( 0.3%) HWCleanup | ||
| 1.2803 ( 3.1%) 0.6899 ( 2.3%) CSE | ||
| 0.0067 ( 0.0%) 0.0036 ( 0.0%) (A) DominanceInfo | ||
| 1.7176 ( 4.2%) 0.8772 ( 3.0%) Canonicalizer | ||
| 0.0135 ( 0.0%) 0.0071 ( 0.0%) HWLegalizeModules | ||
| 0.7930 ( 1.9%) 0.7930 ( 2.7%) HWLegalizeNames | ||
| 1.0232 ( 2.5%) 0.5465 ( 1.8%) 'hw.module' Pipeline | ||
| 1.0033 ( 2.5%) 0.5365 ( 1.8%) PrettifyVerilog | ||
| 1.6437 ( 4.0%) 1.6437 ( 5.6%) ExportVerilog emission | ||
| 0.0029 ( 0.0%) 0.0029 ( 0.0%) Rest | ||
| 40.7142 (100.0%) 29.5479 (100.0%) Total | ||
|
|
||
| { | ||
| totalTime: 32.324, | ||
| maxMemory: 970813440 | ||
| totalTime: 29.587, | ||
| maxMemory: 959102976 | ||
| } |