Skip to content

Commit

Permalink
Deploying to gh-pages from @ b35b2ba 🚀
Browse files Browse the repository at this point in the history
  • Loading branch information
@drom
drom committed Sep 20, 2021
1 parent 5d68005 commit 0eca664
Show file tree
Hide file tree
Showing 8 changed files with 249 additions and 0 deletions.
46 changes: 46 additions & 0 deletions chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2021-09-20.log
View file
@@ -0,0 +1,46 @@
===-------------------------------------------------------------------------===
... Execution time report ...
===-------------------------------------------------------------------------===
Total Execution Time: 20.4308 seconds

----User Time---- ----Wall Time---- ----Name----
5.0393 ( 19.4%) 5.0393 ( 24.7%) FIR Parser
12.2038 ( 46.9%) 8.3156 ( 40.7%) 'firrtl.circuit' Pipeline
2.4448 ( 9.4%) 1.2240 ( 6.0%) 'firrtl.module' Pipeline
2.1889 ( 8.4%) 1.0986 ( 5.4%) CSE
0.0017 ( 0.0%) 0.0010 ( 0.0%) (A) DominanceInfo
0.2504 ( 1.0%) 0.1313 ( 0.6%) LowerCHIRRTL
0.1421 ( 0.5%) 0.1421 ( 0.7%) InferWidths
0.8980 ( 3.5%) 0.8980 ( 4.4%) InferResets
0.0488 ( 0.2%) 0.0488 ( 0.2%) (A) circt::firrtl::InstanceGraph
0.0911 ( 0.4%) 0.0911 ( 0.4%) PrefixModules
0.0456 ( 0.2%) 0.0456 ( 0.2%) (A) circt::firrtl::InstanceGraph
0.7984 ( 3.1%) 0.7984 ( 3.9%) LowerFIRRTLTypes
3.5397 ( 13.6%) 1.7735 ( 8.7%) 'firrtl.module' Pipeline
1.3604 ( 5.2%) 0.7067 ( 3.5%) ExpandWhens
2.1738 ( 8.4%) 1.1101 ( 5.4%) Canonicalizer
0.5901 ( 2.3%) 0.5901 ( 2.9%) Inliner
1.8886 ( 7.3%) 1.8886 ( 9.2%) IMConstProp
0.0456 ( 0.2%) 0.0456 ( 0.2%) (A) circt::firrtl::InstanceGraph
0.0004 ( 0.0%) 0.0004 ( 0.0%) BlackBoxReader
1.7997 ( 6.9%) 0.9017 ( 4.4%) 'firrtl.module' Pipeline
1.7965 ( 6.9%) 0.9000 ( 4.4%) Canonicalizer
1.2108 ( 4.7%) 1.2108 ( 5.9%) LowerFIRRTLToHW
0.2543 ( 1.0%) 0.2543 ( 1.2%) HWMemSimImpl
2.9130 ( 11.2%) 1.4568 ( 7.1%) 'hw.module' Pipeline
0.0633 ( 0.2%) 0.0389 ( 0.2%) HWCleanup
0.9538 ( 3.7%) 0.4822 ( 2.4%) CSE
0.0017 ( 0.0%) 0.0009 ( 0.0%) (A) DominanceInfo
1.8691 ( 7.2%) 0.9490 ( 4.6%) Canonicalizer
0.0152 ( 0.1%) 0.0095 ( 0.0%) HWLegalizeModules
0.4482 ( 1.7%) 0.4482 ( 2.2%) HWLegalizeNames
0.5089 ( 2.0%) 0.2545 ( 1.2%) 'hw.module' Pipeline
0.5045 ( 1.9%) 0.2523 ( 1.2%) PrettifyVerilog
3.4389 ( 13.2%) 3.4389 ( 16.8%) ExportVerilog emission
0.0062 ( 0.0%) 0.0062 ( 0.0%) Rest
26.0297 (100.0%) 20.4308 (100.0%) Total

{
totalTime: 20.478,
maxMemory: 880795648
}
49 changes: 49 additions & 0 deletions ...TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2021-09-20.json
View file
@@ -0,0 +1,49 @@
{
"errors": {
"'table_1_ext'": 1,
"This may be because there's no search path specified with -I<dir>.": 1,
"'table_0_ext'": 1,
"'hi_us_0_ext'": 1,
"'table_ext'": 1,
"'hi_us_ext'": 1,
"'meta_0_0_ext'": 1,
"'data_ext'": 1,
"'ebtb_ext'": 1,
"'btb_0_ext'": 1,
"'meta_0_ext'": 1,
"'rob_debug_inst_mem_1_ext'": 1,
"'meta_2_ext'": 1,
"'tag_array_5_ext'": 1,
"'rob_debug_inst_mem_0_ext'": 1,
"'ghist_0_0_ext'": 1,
"'meta_1_ext'": 1,
"'rob_debug_inst_mem_ext'": 1,
"'ghist_0_ext'": 1,
"'meta_ext'": 1,
"'dataArrayB0Way_0_ext'": 1,
"'tag_array_4_ext'": 1,
"'array_0_0_ext'": 1,
"'tag_array_3_ext'": 1,
"'data_arrays_0_2_ext'": 1,
"'tag_array_2_ext'": 1,
"'data_arrays_0_1_ext'": 1,
"'data_arrays_0_0_ext'": 1,
"'tag_array_0_ext'": 1,
"'tag_array_ext'": 1,
"'data_arrays_0_ext'": 1,
"'plusarg_reader'": 142,
"'l2_tlb_ram_1_ext'": 1,
"'l2_tlb_ram_0_ext'": 1,
"'tag_array_1_ext'": 1,
"'l2_tlb_ram_ext'": 1,
"'cc_banks_0_ext'": 1,
"'cc_dir_ext'": 1,
"'ClockDividerN'": 1,
"'EICG_wrapper'": 1,
"'GenericDigitalOutIOCell'": 9,
"'GenericDigitalInIOCell'": 13
},
"warnings": {
"WIDTH": 25
}
}
46 changes: 46 additions & 0 deletions test1-2021-09-20.log
View file
@@ -0,0 +1,46 @@
===-------------------------------------------------------------------------===
... Execution time report ...
===-------------------------------------------------------------------------===
Total Execution Time: 1.7183 seconds

----User Time---- ----Wall Time---- ----Name----
0.3725 ( 16.8%) 0.3725 ( 21.7%) FIR Parser
1.4890 ( 67.1%) 0.9871 ( 57.4%) 'firrtl.circuit' Pipeline
0.1578 ( 7.1%) 0.0848 ( 4.9%) 'firrtl.module' Pipeline
0.1371 ( 6.2%) 0.0736 ( 4.3%) CSE
0.0000 ( 0.0%) 0.0000 ( 0.0%) (A) DominanceInfo
0.0206 ( 0.9%) 0.0112 ( 0.7%) LowerCHIRRTL
0.0168 ( 0.8%) 0.0168 ( 1.0%) InferWidths
0.0675 ( 3.0%) 0.0675 ( 3.9%) InferResets
0.0034 ( 0.2%) 0.0034 ( 0.2%) (A) circt::firrtl::InstanceGraph
0.0049 ( 0.2%) 0.0049 ( 0.3%) PrefixModules
0.0029 ( 0.1%) 0.0029 ( 0.2%) (A) circt::firrtl::InstanceGraph
0.1469 ( 6.6%) 0.1469 ( 8.6%) LowerFIRRTLTypes
0.8654 ( 39.0%) 0.4364 ( 25.4%) 'firrtl.module' Pipeline
0.1283 ( 5.8%) 0.0667 ( 3.9%) ExpandWhens
0.7371 ( 33.2%) 0.3749 ( 21.8%) Canonicalizer
0.0259 ( 1.2%) 0.0259 ( 1.5%) Inliner
0.0366 ( 1.6%) 0.0366 ( 2.1%) IMConstProp
0.0005 ( 0.0%) 0.0005 ( 0.0%) (A) circt::firrtl::InstanceGraph
0.0000 ( 0.0%) 0.0000 ( 0.0%) BlackBoxReader
0.1668 ( 7.5%) 0.1668 ( 9.7%) 'firrtl.module' Pipeline
0.1668 ( 7.5%) 0.1668 ( 9.7%) Canonicalizer
0.1139 ( 5.1%) 0.1139 ( 6.6%) LowerFIRRTLToHW
0.0000 ( 0.0%) 0.0000 ( 0.0%) HWMemSimImpl
0.1440 ( 6.5%) 0.1440 ( 8.4%) 'hw.module' Pipeline
0.0015 ( 0.1%) 0.0015 ( 0.1%) HWCleanup
0.0439 ( 2.0%) 0.0439 ( 2.6%) CSE
0.0000 ( 0.0%) 0.0000 ( 0.0%) (A) DominanceInfo
0.0976 ( 4.4%) 0.0976 ( 5.7%) Canonicalizer
0.0010 ( 0.0%) 0.0010 ( 0.1%) HWLegalizeModules
0.0089 ( 0.4%) 0.0089 ( 0.5%) HWLegalizeNames
0.0197 ( 0.9%) 0.0197 ( 1.1%) 'hw.module' Pipeline
0.0197 ( 0.9%) 0.0197 ( 1.1%) PrettifyVerilog
0.0708 ( 3.2%) 0.0708 ( 4.1%) ExportVerilog emission
0.0013 ( 0.1%) 0.0013 ( 0.1%) Rest
2.2202 (100.0%) 1.7183 (100.0%) Total

{
totalTime: 1.73,
maxMemory: 68431872
}
4 changes: 4 additions & 0 deletions test1-vlint-2021-09-20.json
View file
@@ -0,0 +1,4 @@
{
"errors": {},
"warnings": {}
}
46 changes: 46 additions & 0 deletions test2-2021-09-20.log
View file
@@ -0,0 +1,46 @@
===-------------------------------------------------------------------------===
... Execution time report ...
===-------------------------------------------------------------------------===
Total Execution Time: 38.6967 seconds

----Wall Time---- ----Name----
4.8188 ( 12.5%) FIR Parser
18.2635 ( 47.2%) 'firrtl.circuit' Pipeline
1.7477 ( 4.5%) 'firrtl.module' Pipeline
1.5728 ( 4.1%) CSE
0.0000 ( 0.0%) (A) DominanceInfo
0.1749 ( 0.5%) LowerCHIRRTL
0.1137 ( 0.3%) InferWidths
0.8558 ( 2.2%) InferResets
0.0267 ( 0.1%) (A) circt::firrtl::InstanceGraph
0.0475 ( 0.1%) PrefixModules
0.0241 ( 0.1%) (A) circt::firrtl::InstanceGraph
0.8635 ( 2.2%) LowerFIRRTLTypes
7.7315 ( 20.0%) 'firrtl.module' Pipeline
1.1083 ( 2.9%) ExpandWhens
6.6232 ( 17.1%) Canonicalizer
0.4804 ( 1.2%) Inliner
1.3512 ( 3.5%) IMConstProp
0.0381 ( 0.1%) (A) circt::firrtl::InstanceGraph
0.0000 ( 0.0%) BlackBoxReader
5.0719 ( 13.1%) 'firrtl.module' Pipeline
5.0719 ( 13.1%) Canonicalizer
3.0464 ( 7.9%) LowerFIRRTLToHW
0.0000 ( 0.0%) HWMemSimImpl
8.6937 ( 22.5%) 'hw.module' Pipeline
0.0933 ( 0.2%) HWCleanup
1.2855 ( 3.3%) CSE
0.0000 ( 0.0%) (A) DominanceInfo
7.2209 ( 18.7%) Canonicalizer
0.0940 ( 0.2%) HWLegalizeModules
0.4285 ( 1.1%) HWLegalizeNames
1.0128 ( 2.6%) 'hw.module' Pipeline
1.0128 ( 2.6%) PrettifyVerilog
2.4307 ( 6.3%) ExportVerilog emission
0.0021 ( 0.0%) Rest
38.6967 (100.0%) Total

{
totalTime: 38.728,
maxMemory: 598671360
}
6 changes: 6 additions & 0 deletions test2-vlint-2021-09-20.json
View file
@@ -0,0 +1,6 @@
{
"errors": {},
"warnings": {
"WIDTH": 6
}
}
46 changes: 46 additions & 0 deletions test3-2021-09-20.log
View file
@@ -0,0 +1,46 @@
===-------------------------------------------------------------------------===
... Execution time report ...
===-------------------------------------------------------------------------===
Total Execution Time: 39.4901 seconds

----User Time---- ----Wall Time---- ----Name----
11.6358 ( 21.4%) 11.6358 ( 29.5%) FIR Parser
28.4578 ( 52.3%) 17.0209 ( 43.1%) 'firrtl.circuit' Pipeline
3.5375 ( 6.5%) 1.9842 ( 5.0%) 'firrtl.module' Pipeline
3.1382 ( 5.8%) 1.7585 ( 4.5%) CSE
0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) DominanceInfo
0.3993 ( 0.7%) 0.2257 ( 0.6%) LowerCHIRRTL
0.2836 ( 0.5%) 0.2836 ( 0.7%) InferWidths
1.5381 ( 2.8%) 1.5381 ( 3.9%) InferResets
0.0799 ( 0.1%) 0.0799 ( 0.2%) (A) circt::firrtl::InstanceGraph
0.1705 ( 0.3%) 0.1705 ( 0.4%) PrefixModules
0.0787 ( 0.1%) 0.0787 ( 0.2%) (A) circt::firrtl::InstanceGraph
1.9460 ( 3.6%) 1.9460 ( 4.9%) LowerFIRRTLTypes
12.3534 ( 22.7%) 6.9116 ( 17.5%) 'firrtl.module' Pipeline
4.1399 ( 7.6%) 2.2844 ( 5.8%) ExpandWhens
8.2134 ( 15.1%) 4.6271 ( 11.7%) Canonicalizer
0.3615 ( 0.7%) 0.3615 ( 0.9%) Inliner
1.2729 ( 2.3%) 1.2729 ( 3.2%) IMConstProp
0.0411 ( 0.1%) 0.0411 ( 0.1%) (A) circt::firrtl::InstanceGraph
0.0000 ( 0.0%) 0.0000 ( 0.0%) BlackBoxReader
4.4374 ( 8.2%) 2.5411 ( 6.4%) 'firrtl.module' Pipeline
4.4373 ( 8.2%) 2.5411 ( 6.4%) Canonicalizer
2.1993 ( 4.0%) 2.1993 ( 5.6%) LowerFIRRTLToHW
1.3466 ( 2.5%) 1.3466 ( 3.4%) HWMemSimImpl
5.2804 ( 9.7%) 2.6618 ( 6.7%) 'hw.module' Pipeline
0.1870 ( 0.3%) 0.0977 ( 0.2%) HWCleanup
2.1653 ( 4.0%) 1.1675 ( 3.0%) CSE
0.0094 ( 0.0%) 0.0054 ( 0.0%) (A) DominanceInfo
2.8380 ( 5.2%) 1.4835 ( 3.8%) Canonicalizer
0.0161 ( 0.0%) 0.0097 ( 0.0%) HWLegalizeModules
1.3651 ( 2.5%) 1.3651 ( 3.5%) HWLegalizeNames
1.8473 ( 3.4%) 1.0113 ( 2.6%) 'hw.module' Pipeline
1.8228 ( 3.3%) 0.9988 ( 2.5%) PrettifyVerilog
2.2154 ( 4.1%) 2.2154 ( 5.6%) ExportVerilog emission
0.0049 ( 0.0%) 0.0049 ( 0.0%) Rest
54.4248 (100.0%) 39.4901 (100.0%) Total

{
totalTime: 39.548,
maxMemory: 970891264
}
6 changes: 6 additions & 0 deletions test3-vlint-2021-09-20.json
View file
@@ -0,0 +1,6 @@
{
"errors": {},
"warnings": {
"WIDTH": 5
}
}

0 comments on commit 0eca664

Please sign in to comment.