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@drom
drom committed Sep 15, 2021
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44 changes: 44 additions & 0 deletions chipyard.TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-2021-09-15.log
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===-------------------------------------------------------------------------===
... Execution time report ...
===-------------------------------------------------------------------------===
Total Execution Time: 19.0777 seconds

----User Time---- ----Wall Time---- ----Name----
4.6440 ( 19.1%) 4.6440 ( 24.3%) FIR Parser
11.4861 ( 47.1%) 7.8177 ( 41.0%) 'firrtl.circuit' Pipeline
2.2978 ( 9.4%) 1.1506 ( 6.0%) 'firrtl.module' Pipeline
2.0456 ( 8.4%) 1.0264 ( 5.4%) CSE
0.0012 ( 0.0%) 0.0007 ( 0.0%) (A) DominanceInfo
0.2462 ( 1.0%) 0.1252 ( 0.7%) LowerCHIRRTL
0.1275 ( 0.5%) 0.1275 ( 0.7%) InferWidths
0.8353 ( 3.4%) 0.8353 ( 4.4%) InferResets
0.0428 ( 0.2%) 0.0428 ( 0.2%) (A) circt::firrtl::InstanceGraph
0.7445 ( 3.1%) 0.7445 ( 3.9%) LowerFIRRTLTypes
3.3417 ( 13.7%) 1.6734 ( 8.8%) 'firrtl.module' Pipeline
1.2737 ( 5.2%) 0.6495 ( 3.4%) ExpandWhens
2.0630 ( 8.5%) 1.0415 ( 5.5%) Canonicalizer
0.5558 ( 2.3%) 0.5558 ( 2.9%) Inliner
1.8762 ( 7.7%) 1.8762 ( 9.8%) IMConstProp
0.0481 ( 0.2%) 0.0481 ( 0.3%) (A) circt::firrtl::InstanceGraph
0.0003 ( 0.0%) 0.0003 ( 0.0%) BlackBoxReader
1.6919 ( 6.9%) 0.8477 ( 4.4%) 'firrtl.module' Pipeline
1.6887 ( 6.9%) 0.8463 ( 4.4%) Canonicalizer
1.1299 ( 4.6%) 1.1299 ( 5.9%) LowerFIRRTLToHW
0.2377 ( 1.0%) 0.2377 ( 1.2%) HWMemSimImpl
2.7677 ( 11.4%) 1.3839 ( 7.3%) 'hw.module' Pipeline
0.0577 ( 0.2%) 0.0309 ( 0.2%) HWCleanup
0.9016 ( 3.7%) 0.4677 ( 2.5%) CSE
0.0017 ( 0.0%) 0.0008 ( 0.0%) (A) DominanceInfo
1.7841 ( 7.3%) 0.9063 ( 4.8%) Canonicalizer
0.0139 ( 0.1%) 0.0070 ( 0.0%) HWLegalizeModules
0.4347 ( 1.8%) 0.4347 ( 2.3%) HWLegalizeNames
0.4831 ( 2.0%) 0.2416 ( 1.3%) 'hw.module' Pipeline
0.4772 ( 2.0%) 0.2397 ( 1.3%) PrettifyVerilog
3.1763 ( 13.0%) 3.1763 ( 16.6%) ExportVerilog emission
0.0057 ( 0.0%) 0.0057 ( 0.0%) Rest
24.3715 (100.0%) 19.0777 (100.0%) Total

{
totalTime: 19.123,
maxMemory: 880254976
}
49 changes: 49 additions & 0 deletions ...TestHarness.RocketSmall1Medium1Big1_BoomMedium1Large1Mega1.top.v.lo-vlint-2021-09-15.json
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44 changes: 44 additions & 0 deletions test1-2021-09-15.log
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===-------------------------------------------------------------------------===
... Execution time report ...
===-------------------------------------------------------------------------===
Total Execution Time: 1.5595 seconds

----User Time---- ----Wall Time---- ----Name----
0.3382 ( 16.8%) 0.3382 ( 21.7%) FIR Parser
1.3434 ( 66.9%) 0.8944 ( 57.3%) 'firrtl.circuit' Pipeline
0.1655 ( 8.2%) 0.0914 ( 5.9%) 'firrtl.module' Pipeline
0.1358 ( 6.8%) 0.0705 ( 4.5%) CSE
0.0000 ( 0.0%) 0.0000 ( 0.0%) (A) DominanceInfo
0.0297 ( 1.5%) 0.0209 ( 1.3%) LowerCHIRRTL
0.0144 ( 0.7%) 0.0144 ( 0.9%) InferWidths
0.0595 ( 3.0%) 0.0595 ( 3.8%) InferResets
0.0028 ( 0.1%) 0.0028 ( 0.2%) (A) circt::firrtl::InstanceGraph
0.1354 ( 6.7%) 0.1354 ( 8.7%) LowerFIRRTLTypes
0.7658 ( 38.1%) 0.3909 ( 25.1%) 'firrtl.module' Pipeline
0.0990 ( 4.9%) 0.0534 ( 3.4%) ExpandWhens
0.6668 ( 33.2%) 0.3375 ( 21.6%) Canonicalizer
0.0264 ( 1.3%) 0.0264 ( 1.7%) Inliner
0.0359 ( 1.8%) 0.0359 ( 2.3%) IMConstProp
0.0004 ( 0.0%) 0.0004 ( 0.0%) (A) circt::firrtl::InstanceGraph
0.0000 ( 0.0%) 0.0000 ( 0.0%) BlackBoxReader
0.1400 ( 7.0%) 0.1400 ( 9.0%) 'firrtl.module' Pipeline
0.1400 ( 7.0%) 0.1400 ( 9.0%) Canonicalizer
0.1069 ( 5.3%) 0.1069 ( 6.9%) LowerFIRRTLToHW
0.0000 ( 0.0%) 0.0000 ( 0.0%) HWMemSimImpl
0.1251 ( 6.2%) 0.1251 ( 8.0%) 'hw.module' Pipeline
0.0013 ( 0.1%) 0.0013 ( 0.1%) HWCleanup
0.0337 ( 1.7%) 0.0337 ( 2.2%) CSE
0.0000 ( 0.0%) 0.0000 ( 0.0%) (A) DominanceInfo
0.0891 ( 4.4%) 0.0891 ( 5.7%) Canonicalizer
0.0010 ( 0.1%) 0.0010 ( 0.1%) HWLegalizeModules
0.0093 ( 0.5%) 0.0093 ( 0.6%) HWLegalizeNames
0.0193 ( 1.0%) 0.0193 ( 1.2%) 'hw.module' Pipeline
0.0193 ( 1.0%) 0.0193 ( 1.2%) PrettifyVerilog
0.0652 ( 3.2%) 0.0652 ( 4.2%) ExportVerilog emission
0.0010 ( 0.1%) 0.0010 ( 0.1%) Rest
2.0086 (100.0%) 1.5595 (100.0%) Total

{
totalTime: 1.57,
maxMemory: 68186112
}
4 changes: 4 additions & 0 deletions test1-vlint-2021-09-15.json
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{
"errors": {},
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44 changes: 44 additions & 0 deletions test2-2021-09-15.log
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===-------------------------------------------------------------------------===
... Execution time report ...
===-------------------------------------------------------------------------===
Total Execution Time: 36.3227 seconds

----Wall Time---- ----Name----
4.6548 ( 12.8%) FIR Parser
17.1694 ( 47.3%) 'firrtl.circuit' Pipeline
1.6442 ( 4.5%) 'firrtl.module' Pipeline
1.4635 ( 4.0%) CSE
0.0000 ( 0.0%) (A) DominanceInfo
0.1806 ( 0.5%) LowerCHIRRTL
0.1079 ( 0.3%) InferWidths
0.8096 ( 2.2%) InferResets
0.0233 ( 0.1%) (A) circt::firrtl::InstanceGraph
0.8006 ( 2.2%) LowerFIRRTLTypes
7.3505 ( 20.2%) 'firrtl.module' Pipeline
1.0344 ( 2.8%) ExpandWhens
6.3161 ( 17.4%) Canonicalizer
0.4707 ( 1.3%) Inliner
1.2674 ( 3.5%) IMConstProp
0.0326 ( 0.1%) (A) circt::firrtl::InstanceGraph
0.0000 ( 0.0%) BlackBoxReader
4.7185 ( 13.0%) 'firrtl.module' Pipeline
4.7185 ( 13.0%) Canonicalizer
2.8058 ( 7.7%) LowerFIRRTLToHW
0.0000 ( 0.0%) HWMemSimImpl
8.0777 ( 22.2%) 'hw.module' Pipeline
0.0882 ( 0.2%) HWCleanup
1.1795 ( 3.2%) CSE
0.0000 ( 0.0%) (A) DominanceInfo
6.7226 ( 18.5%) Canonicalizer
0.0874 ( 0.2%) HWLegalizeModules
0.3848 ( 1.1%) HWLegalizeNames
1.0075 ( 2.8%) 'hw.module' Pipeline
1.0075 ( 2.8%) PrettifyVerilog
2.2204 ( 6.1%) ExportVerilog emission
0.0021 ( 0.0%) Rest
36.3227 (100.0%) Total

{
totalTime: 36.353,
maxMemory: 640880640
}
6 changes: 6 additions & 0 deletions test2-vlint-2021-09-15.json
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{
"errors": {},
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"WIDTH": 6
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44 changes: 44 additions & 0 deletions test3-2021-09-15.log
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===-------------------------------------------------------------------------===
... Execution time report ...
===-------------------------------------------------------------------------===
Total Execution Time: 36.4187 seconds

----User Time---- ----Wall Time---- ----Name----
10.6552 ( 21.2%) 10.6552 ( 29.3%) FIR Parser
26.7645 ( 53.2%) 15.9429 ( 43.8%) 'firrtl.circuit' Pipeline
3.4032 ( 6.8%) 1.8864 ( 5.2%) 'firrtl.module' Pipeline
2.9938 ( 6.0%) 1.6600 ( 4.6%) CSE
0.0000 ( 0.0%) 0.0000 ( 0.0%) (A) DominanceInfo
0.4094 ( 0.8%) 0.2264 ( 0.6%) LowerCHIRRTL
0.2879 ( 0.6%) 0.2879 ( 0.8%) InferWidths
1.4608 ( 2.9%) 1.4608 ( 4.0%) InferResets
0.0783 ( 0.2%) 0.0783 ( 0.2%) (A) circt::firrtl::InstanceGraph
1.8329 ( 3.6%) 1.8329 ( 5.0%) LowerFIRRTLTypes
11.8258 ( 23.5%) 6.5975 ( 18.1%) 'firrtl.module' Pipeline
4.0286 ( 8.0%) 2.2168 ( 6.1%) ExpandWhens
7.7971 ( 15.5%) 4.3807 ( 12.0%) Canonicalizer
0.3540 ( 0.7%) 0.3540 ( 1.0%) Inliner
1.1750 ( 2.3%) 1.1750 ( 3.2%) IMConstProp
0.0409 ( 0.1%) 0.0409 ( 0.1%) (A) circt::firrtl::InstanceGraph
0.0000 ( 0.0%) 0.0000 ( 0.0%) BlackBoxReader
4.1480 ( 8.3%) 2.3376 ( 6.4%) 'firrtl.module' Pipeline
4.1480 ( 8.3%) 2.3376 ( 6.4%) Canonicalizer
1.8923 ( 3.8%) 1.8923 ( 5.2%) LowerFIRRTLToHW
1.1852 ( 2.4%) 1.1852 ( 3.3%) HWMemSimImpl
4.5839 ( 9.1%) 2.3305 ( 6.4%) 'hw.module' Pipeline
0.1696 ( 0.3%) 0.0866 ( 0.2%) HWCleanup
1.8774 ( 3.7%) 0.9984 ( 2.7%) CSE
0.0086 ( 0.0%) 0.0048 ( 0.0%) (A) DominanceInfo
2.4428 ( 4.9%) 1.2392 ( 3.4%) Canonicalizer
0.0146 ( 0.0%) 0.0078 ( 0.0%) HWLegalizeModules
1.1365 ( 2.3%) 1.1365 ( 3.1%) HWLegalizeNames
1.5511 ( 3.1%) 0.8498 ( 2.3%) 'hw.module' Pipeline
1.5262 ( 3.0%) 0.8373 ( 2.3%) PrettifyVerilog
2.3977 ( 4.8%) 2.3977 ( 6.6%) ExportVerilog emission
0.0028 ( 0.0%) 0.0028 ( 0.0%) Rest
50.2720 (100.0%) 36.4187 (100.0%) Total

{
totalTime: 36.48,
maxMemory: 974143488
}
6 changes: 6 additions & 0 deletions test3-vlint-2021-09-15.json
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{
"errors": {},
"warnings": {
"WIDTH": 5
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}

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