Update version numbers and CHANGELOGs

clash-lang · Sep 14, 2015 · 3ace06d · 3ace06d
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diff --git a/clash-ghc/CHANGELOG.md b/clash-ghc/CHANGELOG.md
@@ -1,5 +1,17 @@
 # Changelog for the [`clash-ghc`](http://hackage.haskell.org/package/clash-ghc) package
 
+## 0.5.14 *September 14th 2015*
+* New features:
+  * Completely unroll "definitions" of some higher-order primitives with non-representable argument or result vectors:
+    It is now possible to translate e.g. `f xs ys = zipWith ($) (map (+) xs) ys :: Vec 4 Int -> Vec 4 Int -> Vec 4 Int`
+
+* Fixes bugs:
+  * Converting Bool to Unsigned generates broken VHDL [#77](https://github.com/clash-lang/clash-compiler/issues/77)
+  * `topLet` transformation erroneously not performed in a top-down traversal
+  * Specialisation limit unchecked on types and constants
+  * Vector of functions cannot be translated [#25](https://github.com/clash-lang/clash-compiler/issues/25 )
+  * CLaSH fails to generate VHDL when map is applied [#78](https://github.com/clash-lang/clash-compiler/issues/78)
+
 ## 0.5.13 *September 8th 2015*
 * Fixes bugs:
   * Cannot translate GHC `MachLabel` literal

diff --git a/clash-ghc/clash-ghc.cabal b/clash-ghc/clash-ghc.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-ghc
-Version:              0.5.13
+Version:              0.5.14
 Synopsis:             CAES Language for Synchronous Hardware
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -94,10 +94,10 @@ Executable clash
                       unbound-generics          >= 0.1 && < 0.3,
                       unordered-containers      >= 0.2.1.0,
 
-                      clash-lib                 >= 0.5.11 && < 0.6,
-                      clash-systemverilog       >= 0.5.8,
-                      clash-vhdl                >= 0.5.10,
-                      clash-verilog             >= 0.5.8,
+                      clash-lib                 >= 0.5.12 && < 0.6,
+                      clash-systemverilog       >= 0.5.9,
+                      clash-vhdl                >= 0.5.11,
+                      clash-verilog             >= 0.5.9,
                       clash-prelude             >= 0.9.2,
                       ghc-typelits-natnormalise >= 0.3
 

diff --git a/clash-lib/CHANGELOG.md b/clash-lib/CHANGELOG.md
@@ -1,5 +1,16 @@
 # Changelog for the [`clash-lib`](http://hackage.haskell.org/package/clash-lib) package
 
+## 0.5.12 *September 14th 2015*
+* New features:
+  * Completely unroll "definitions" of some higher-order primitives with non-representable argument or result vectors:
+    It is now possible to translate e.g. `f xs ys = zipWith ($) (map (+) xs) ys :: Vec 4 Int -> Vec 4 Int -> Vec 4 Int`
+
+* Fixes bugs:
+  * `topLet` transformation erroneously not performed in a top-down traversal
+  * Specialisation limit unchecked on types and constants
+  * Vector of functions cannot be translated [#25](https://github.com/clash-lang/clash-compiler/issues/25 )
+  * CLaSH fails to generate VHDL when map is applied [#78](https://github.com/clash-lang/clash-compiler/issues/78)
+
 ## 0.5.11 *September 7th 2015*
 * Fixes bugs:
   * Clash running out of memory on Simple-ish project [#70](https://github.com/clash-lang/clash-compiler/issues/70)

diff --git a/clash-lib/clash-lib.cabal b/clash-lib/clash-lib.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-lib
-Version:              0.5.11
+Version:              0.5.12
 Synopsis:             CAES Language for Synchronous Hardware - As a Library
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that

diff --git a/clash-systemverilog/CHANGELOG.md b/clash-systemverilog/CHANGELOG.md
@@ -1,5 +1,8 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+## 0.5.9 *September 14 2015*
+* Support for clash-lib-0.5.12
+
 ## 0.5.8 *September 7th 2015*
 * Fixes bugs:
   * Fix primitive for CLaSH.Sized.Internal.Signed.size# [#72](https://github.com/clash-lang/clash-compiler/pull/72)

diff --git a/clash-systemverilog/clash-systemverilog.cabal b/clash-systemverilog/clash-systemverilog.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-systemverilog
-Version:              0.5.8
+Version:              0.5.9
 Synopsis:             CAES Language for Synchronous Hardware - SystemVerilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -93,7 +93,7 @@ Library
                       ViewPatterns
 
   Build-depends:      base                    >= 4.6.0.1 && < 5,
-                      clash-lib               >= 0.5.8,
+                      clash-lib               >= 0.5.12,
                       clash-prelude           >= 0.9,
                       fgl                     >= 5.4.2.4,
                       lens                    >= 3.9.2,

diff --git a/clash-verilog/CHANGELOG.md b/clash-verilog/CHANGELOG.md
@@ -1,5 +1,8 @@
 # Changelog for the [`clash-systemverilog`](http://hackage.haskell.org/package/clash-systemverilog) package
 
+## 0.5.9 *September 14th 2015*
+* Support for clash-lib-0.5.12
+
 ## 0.5.8 *September 7th 2015*
 * Fixes bugs:
   * Fix primitive for CLaSH.Sized.Internal.Signed.size# [#72](https://github.com/clash-lang/clash-compiler/pull/72)

diff --git a/clash-verilog/clash-verilog.cabal b/clash-verilog/clash-verilog.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-verilog
-Version:              0.5.8
+Version:              0.5.9
 Synopsis:             CAES Language for Synchronous Hardware - Verilog backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -93,7 +93,7 @@ Library
                       ViewPatterns
 
   Build-depends:      base                    >= 4.6.0.1 && < 5,
-                      clash-lib               >= 0.5.8,
+                      clash-lib               >= 0.5.12,
                       clash-prelude           >= 0.9,
                       fgl                     >= 5.4.2.4,
                       lens                    >= 3.9.2,

diff --git a/clash-vhdl/CHANGELOG.md b/clash-vhdl/CHANGELOG.md
@@ -1,5 +1,10 @@
 # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package
 
+## 0.5.11 *September 14th 2015*
+* Support for clash-lib-0.5.12
+* Fixes bugs:
+  * Converting Bool to Unsigned generates broken VHDL [#77](https://github.com/clash-lang/clash-compiler/issues/77)
+
 ## 0.5.10 *September 8th 2015*
 * Fixes bugs:
   * Maybe (Index n) not translatable to VHDL [#75](https://github.com/clash-lang/clash-compiler/issues/75)

diff --git a/clash-vhdl/clash-vhdl.cabal b/clash-vhdl/clash-vhdl.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-vhdl
-Version:              0.5.10
+Version:              0.5.11
 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -93,7 +93,7 @@ Library
                       ViewPatterns
 
   Build-depends:      base                    >= 4.6.0.1 && < 5,
-                      clash-lib               >= 0.5.8,
+                      clash-lib               >= 0.5.12,
                       clash-prelude           >= 0.9,
                       fgl                     >= 5.4.2.4,
                       lens                    >= 3.9.2,