SystemVerilog: Bool is a scalar type

Fixes #569
clash-lang · Aug 14, 2019 · 97a9047 · 97a9047
1 parent 3aee0c5
commit 97a9047
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Showing 2 changed files with 1 addition and 2 deletions.
diff --git a/clash-lib/src/Clash/Backend/SystemVerilog.hs b/clash-lib/src/Clash/Backend/SystemVerilog.hs
@@ -298,7 +298,6 @@ mkTyPackage_ modName hwtys = do
       | otherwise                        = ty1 == ty2
 
     isUnsigned :: HWType -> Bool
-    isUnsigned Bool                = True
     isUnsigned (Unsigned _)        = True
     isUnsigned (BitVector _)       = True
     isUnsigned (Index _)           = True

diff --git a/testsuite/Main.hs b/testsuite/Main.hs
@@ -64,7 +64,7 @@ runClashTest =
     , clashTestGroup "Unit"
       [ clashTestGroup "Basic"
         [ -- TODO: Enable AES test on SystemVerilog. See issue #569.
-          runTest ("tests" </> "shouldwork" </> "Basic") (defBuild \\ [SystemVerilog]) [] "AES"                 ([""],"topEntity",False)
+          runTest ("tests" </> "shouldwork" </> "Basic") defBuild [] "AES"                 ([""],"topEntity",False)
         , runTest ("tests" </> "shouldwork" </> "Basic") defBuild [] "BangData"            ([""],"topEntity",False)
         , runTest ("tests" </> "shouldwork" </> "Basic") defBuild [] "Trace"               ([""],"topEntity",False)
         , runTest ("tests" </> "shouldwork" </> "Basic") defBuild [] "ByteSwap32"          (["","testBench"],"testBench",True)