Generate qsys files for altpll and alterapll

Fixes #545
clash-lang · Jan 19, 2020 · c82621e · c82621e
1 parent 80ee6c2
commit c82621e
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Showing 2 changed files with 56 additions and 4 deletions.
diff --git a/clash-lib/prims/common/Clash_Intel_ClockGen.json b/clash-lib/prims/common/Clash_Intel_ClockGen.json
@@ -2,6 +2,12 @@
     { "name"      : "Clash.Intel.ClockGen.altpll"
     , "workInfo"  : "Always"
     , "kind"      : "Declaration"
+    , "includes"  : [ {"extension": "qsys"
+                      ,"name": "altpll"
+                      ,"format": "Haskell"
+                      ,"templateFunction": "Clash.Primitives.Intel.ClockGen.altpllqsysTF"
+                      }
+                    ]
     , "format"    : "Haskell"
     , "templateFunction" : "Clash.Primitives.Intel.ClockGen.altpllTF"
     }

diff --git a/clash-lib/src/Clash/Primitives/Intel/ClockGen.hs b/clash-lib/src/Clash/Primitives/Intel/ClockGen.hs
@@ -7,6 +7,7 @@
 -}
 
 {-# LANGUAGE OverloadedStrings #-}
+{-# LANGUAGE QuasiQuotes       #-}
 {-# LANGUAGE ViewPatterns      #-}
 
 module Clash.Primitives.Intel.ClockGen where
@@ -19,6 +20,7 @@ import Clash.Netlist.Types
 import Control.Monad.State
 
 import Data.Semigroup.Monad
+import qualified Data.String.Interpolate.IsString as I
 import Data.Text.Prettyprint.Doc.Extra
 
 import qualified Data.Text as TextS
@@ -34,6 +36,17 @@ altpllTF = TemplateFunction used valid altpllTemplate
     = True
   valid _ = False
 
+altpllqsysTF :: TemplateFunction
+altpllqsysTF = TemplateFunction used valid altpllqsysTemplate
+ where
+  used = [0,1,2]
+  valid bbCtx
+    | [(nm,_,_),_,_] <- bbInputs bbCtx
+    , Just _ <- exprToString nm
+    , (Identifier _ Nothing,Product {}) <- bbResult bbCtx
+    = True
+  valid _ = False
+
 alteraPllTF :: TemplateFunction
 alteraPllTF = TemplateFunction used valid alteraPllTemplate
  where
@@ -92,14 +105,14 @@ altpllTemplate bbCtx = do
  pllOut <- mkId "pllOut"
  locked <- mkId "locked"
  pllLock <- mkId "pllLock"
- alteraPll <- mkId "altpll"
- alteraPll_inst <- mkId "altpll_inst"
+ alteraPll <- mkId "altpll_block"
+ alteraPll_inst <- mkId instname0
  getMon $ blockDecl alteraPll
   [ NetDecl Nothing locked  Bit
   , NetDecl Nothing pllLock Bool
   , NetDecl Nothing pllOut clkOutTy
   , InstDecl Comp Nothing compName alteraPll_inst []
-      [(Identifier "inclk0" Nothing,In,clkTy,clk)
+      [(Identifier "clk" Nothing,In,clkTy,clk)
       ,(Identifier "areset" Nothing,In,rstTy,rst)
       ,(Identifier "c0" Nothing,Out,clkOutTy,Identifier pllOut Nothing)
       ,(Identifier "locked" Nothing,Out,Bit,Identifier locked Nothing)]
@@ -115,5 +128,38 @@ altpllTemplate bbCtx = do
   [(nm,_,_),(clk,clkTy,_),(rst,rstTy,_)] = bbInputs bbCtx
   (Identifier result Nothing,resTy@(Product _ _ [clkOutTy,_])) = bbResult bbCtx
   Just nm' = exprToString nm
-  compName = TextS.pack nm'
+  instname0 = TextS.pack nm'
+  compName = head (bbQsysIncName bbCtx)
 
+
+altpllqsysTemplate
+  :: Backend s
+  => BlackBoxContext
+  -> State s Doc
+altpllqsysTemplate _bbCtx = pure bbText
+ where
+  bbText = [I.i|<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+  <module
+    name="altpll0"
+    kind="altpll"
+    enabled="1"
+    autoexport="1">
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+  <parameter name="BANDWIDTH" value="" />
+  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+  <parameter name="CLK0_DIVIDE_BY" value="1" />
+  <parameter name="CLK0_DUTY_CYCLE" value="50" />
+  <parameter name="CLK0_MULTIPLY_BY" value="2" />
+  <parameter name="CLK0_PHASE_SHIFT" value="0" />
+  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+  <parameter name="OPERATION_MODE" value="NORMAL" />
+  <parameter name="PLL_TYPE" value="AUTO" />
+  <parameter name="PORT_ARESET" value="PORT_USED" />
+  <parameter name="PORT_INCLK0" value="PORT_USED" />
+  <parameter name="PORT_LOCKED" value="PORT_USED" />
+  <parameter name="PORT_clk0" value="PORT_USED" />
+  <parameter name="HIDDEN_PRIVATES">PT#EFF_OUTPUT_FREQ_VALUE0 100.000000</parameter>
+  </module>
+</system>|]