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Fix Xilinx clock wizard, add Tcl IP generation
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CHANGED: Remove `Asynchronous` constraint from Xilinx `clockWizard` and `clockWizardDifferential`. Originally intended to signal that these functions react synchronously to the incoming reset and that the outgoing lock signal is an asynchronous signal. Since synchronous reset signals are a subset of asynchronous reset signals this constraint on the input is vacuous. The constraint on the lock output does not convey this information at all and is wrong. Note that it is still necessary to synchronize the lock output in your design. | ||
FIXED: Fix Xilinx ClockGen primitives. The port names of the Xilinx ClockGen primitives are now lowercase. The type of the lock output of Xilinx `clockWizard` and `clockWizardDifferential` is now `Signal Bool` instead of `Enable`, which was not the correct type here as a circuit should be kept in reset while the clock is stabilizing. This also fixes a polarity mismatch between hardware (and HDL simulation) and Haskell simulation. The lock signal is now also correctly resampled to the output domain. | ||
ADD: Add Tcl generation of Xilinx `clockWizard` and `clockWizardDifferential`. This moves the responsibility of MMCM component generation from the user to `clashConnector.tcl`. |
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{-| | ||
Copyright : (C) 2023, QBayLogic B.V. | ||
License : BSD2 (see the file LICENSE) | ||
Maintainer : QBayLogic B.V. <devops@qbaylogic.com> | ||
Blackbox template functions for | ||
Clash.Xilinx.ClockGen.{clockWizard,clockWizardDifferential} | ||
-} | ||
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{-# LANGUAGE QuasiQuotes #-} | ||
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module Clash.Primitives.Xilinx.ClockGen where | ||
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import Control.Monad.State (State) | ||
import qualified Data.String.Interpolate as I | ||
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import Clash.Signal (periodToHz) | ||
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import Clash.Backend (Backend) | ||
import Clash.Netlist.BlackBox.Util (exprToString) | ||
import Clash.Netlist.Types | ||
import Clash.Netlist.Util (stripVoid) | ||
import Data.Text.Prettyprint.Doc.Extra (Doc) | ||
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clockWizardTclTF :: TemplateFunction | ||
clockWizardTclTF = | ||
TemplateFunction used valid (clockWizardTclTemplate False) | ||
where | ||
knownDomIn = 0 | ||
knownDomOut = 1 | ||
name = 2 | ||
-- clk = 3 | ||
-- rst = 4 | ||
used = [knownDomIn, knownDomOut, name] | ||
valid = const True | ||
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clockWizardDifferentialTclTF :: TemplateFunction | ||
clockWizardDifferentialTclTF = | ||
TemplateFunction used valid (clockWizardTclTemplate True) | ||
where | ||
knownDomIn = 0 | ||
knownDomOut = 1 | ||
name = 2 | ||
-- clkN = 3 | ||
-- clkP = 4 | ||
-- rst = 5 | ||
used = [knownDomIn, knownDomOut, name] | ||
valid = const True | ||
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clockWizardTclTemplate | ||
:: Backend s | ||
=> Bool | ||
-> BlackBoxContext | ||
-> State s Doc | ||
clockWizardTclTemplate isDifferential bbCtx | ||
| (_,stripVoid -> (KnownDomain _ clkInPeriod _ _ _ _),_) <- bbInputs bbCtx !! 0 | ||
, (_,stripVoid -> (KnownDomain _ clkOutPeriod _ _ _ _),_) <- bbInputs bbCtx !! 1 | ||
, (nm,_,_) <- bbInputs bbCtx !! 2 | ||
, [(Identifier _ Nothing,Product {})] <- bbResults bbCtx | ||
, Just compName <- exprToString nm | ||
= | ||
let | ||
clkInFreq :: Double | ||
clkInFreq = periodToHz (fromInteger clkInPeriod) / 1e6 | ||
clkOutFreq :: Double | ||
clkOutFreq = periodToHz (fromInteger clkOutPeriod) / 1e6 | ||
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differentialPinString = if isDifferential | ||
then "Differential_clock_capable_pin" | ||
else "Single_ended_clock_capable_pin" | ||
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bbText = [I.__i| | ||
namespace eval $tclIface { | ||
variable api 1 | ||
variable scriptPurpose createIp | ||
variable ipName {#{compName}} | ||
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proc createIp {ipName0 args} { | ||
create_ip \\ | ||
-name clk_wiz \\ | ||
-vendor xilinx.com \\ | ||
-library ip \\ | ||
-version 6.0 \\ | ||
-module_name $ipName0 \\ | ||
{*}$args | ||
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set_property \\ | ||
-dict [list \\ | ||
CONFIG.PRIM_SOURCE #{differentialPinString} \\ | ||
CONFIG.PRIM_IN_FREQ #{clkInFreq} \\ | ||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ #{clkOutFreq} \\ | ||
] [get_ips $ipName0] | ||
return | ||
} | ||
}|] | ||
in pure bbText | ||
| otherwise | ||
= error ("clockWizardTclTemplate: bad bbContext: " <> show bbCtx) |
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