Add test for #1240

PR #1354 fixes #1240
clash-lang · Jun 4, 2020 · e8eb313 · e8eb313
1 parent a30be39
commit e8eb313
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diff --git a/changelog/2020-05-28T16_39_31+02_00_fix1240 b/changelog/2020-05-28T16_39_31+02_00_fix1240
@@ -0,0 +1 @@
+FIXES: Added blackbox implementation for 'Clash.Sized.Vector.iterateI', hence making it usable as a register reset value [#1240](https://github.com/clash-lang/clash-compiler/issues/1240)
diff --git a/tests/shouldwork/Basic/T1240.hs b/tests/shouldwork/Basic/T1240.hs
@@ -0,0 +1,9 @@
+module T1240 where
+
+import Clash.Prelude
+
+topEntity
+  :: SystemClockResetEnable
+  => Signal System (Vec 1 Bool)
+  -> Signal System (Vec 1 Bool)
+topEntity = register @System $(lift (iterate d1 not True))
diff --git a/testsuite/Main.hs b/testsuite/Main.hs
@@ -273,6 +273,7 @@ runClashTest = defaultMain $ clashTestRoot
           , topEntities=TopEntities ["top1"]
           }
         , runTest "T1012" def{hdlSim=False}
+        , runTest "T1240" def{hdlSim=False}
         , runTest "T1242" def{hdlSim=False}
         , runTest "T1254" def{hdlTargets=[VHDL,SystemVerilog],hdlSim=False}
         , runTest "T1292" def{hdlTargets=[VHDL]}