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Add 'RenderVoid' option to blackboxes
Void data (e.g., `Index 1`, `BitVector 0`, `()`) results in zero-width vectors in HDL. HDL tools handle these constructs poorly. To work around that 01843d3 added void-filtering to Clash. As a consequence, any functions solely generating a void construct aren't rendered at all. Often, this is okay: functions yielding voids are generally the result of a generalization and don't perform any actually work when instantiated with a void. _Sometimes_ though, we would like to generate them: * In the case of `BiSignal`s, one would like to completely remove any `BiSignalOut`s from the HDL, as the corresponding `BiSignalIn` will already be converted to an `inout` wire. * (SystemVerilog) Assertions don't carry any "out" signals. They construct a comment instructing the simulator / verification tool to check some property. Clash simulation can't support this though: functions without outputs simply do not exist. In this case, we'd like to mark an "assertion result" as void, so it would get filtered in HDL. See #864 for more information. * Some `IO ()` actions as described in #815 must result in HDL. Like the previous two features, `IO ()` would get filtered though. This commit allows blackboxes to specify whether they would like to be rendered even if their result is void. Note that any blackboxes specifying this must make sure that they do not assign anything to their result - as this is zero bits, Clash won't generate any signal declarations for it. As a happy coincidence, this removes the need for special support for BiSignalOut in the compiler.
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Original file line number | Diff line number | Diff line change |
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{-# LANGUAGE BangPatterns #-} | ||
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module ZeroWidth where | ||
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import qualified Prelude as P | ||
import Control.Monad (forM_) | ||
import Clash.Annotations.Primitive | ||
import Clash.Prelude | ||
import GHC.Exts | ||
import Data.String.Interpolate (i) | ||
import Data.String.Interpolate.Util (unindent) | ||
import Data.List (isInfixOf) | ||
import System.Environment (getArgs) | ||
import System.FilePath ((</>), takeDirectory) | ||
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luckyNumber, question, answer :: String | ||
luckyNumber = "Your lucky number is 3552664958674928." | ||
question = "What lies on the bottom of the ocean and twitches?" | ||
answer = "A nervous wreck." | ||
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-- | Inserts given comment in HDL. Returns "nothing". | ||
comment :: String -> () | ||
comment !_s = () | ||
{-# NOINLINE comment #-} | ||
{-# ANN comment (InlinePrimitive VHDL $ unindent [i| | ||
[ { "BlackBox" : | ||
{ "name" : "ZeroWidth.comment" | ||
, "kind" : "Declaration" | ||
, "renderVoid": "RenderVoid" | ||
, "template" : "~NAME[0]" | ||
} | ||
} | ||
] |] | ||
) #-} | ||
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implicitComment :: Int -> () | ||
implicitComment n = | ||
case n of | ||
5 -> () | ||
_ -> | ||
comment question | ||
{-# NOINLINE implicitComment #-} | ||
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topEntity :: Int -> (Int, (), ()) | ||
topEntity a = (succ a, comment luckyNumber, implicitComment a) | ||
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mainHDL :: String -> String -> IO () | ||
mainHDL topFile implFile = do | ||
[topDir] <- getArgs | ||
contentTopEntity <- readFile (takeDirectory topDir </> topFile) | ||
contentImplicitComment <- readFile (takeDirectory topDir </> implFile) | ||
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if luckyNumber `isInfixOf` contentTopEntity then | ||
pure () | ||
else | ||
error $ "Expected:\n\n" P.++ luckyNumber | ||
P.++ "\n\nBut did not find it in:\n\n" P.++ contentTopEntity | ||
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if question `isInfixOf` contentImplicitComment then | ||
pure () | ||
else | ||
error $ "Expected:\n\n" P.++ question | ||
P.++ "\n\nBut did not find it in:\n\n" P.++ contentImplicitComment | ||
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mainSystemVerilog, mainVerilog, mainVHDL :: IO () | ||
mainSystemVerilog = error "NYI" | ||
mainVerilog = error "NYI" | ||
mainVHDL = mainHDL "topentity.vhdl" "implicitcomment.vhdl" |
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