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Sample vs simulate behaviour #2029

Answered by martijnbastiaan
ra1u asked this question in Q&A
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Is this bahaviour expected (notice difference between test1 and test2 output )?

Yes, insofar as that the documentation of sample says:

If the given component has not yet been given a clock, reset, or enable line, sample will supply them. The reset will be asserted for a single cycle. sample will not drop the value produced by the circuit while the reset was asserted. If you want this, or if you want more than a single cycle reset, consider using sampleWithReset.

Documentation of simulate:

Where 'System' denotes the /domain/ to simulate on. The reset line is asserted for a single cycle. The first value is therefore supplied twice to the circuit: once while reset is high, and once dire…

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