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Bug in DEC transformation throws CLaSH into an endless loop #140

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christiaanb opened this Issue Apr 4, 2016 · 0 comments

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christiaanb commented Apr 4, 2016

The following code:

module Loopbug where

import CLaSH.Prelude

type FPM    = SFixed 5 0 

valC                            = 1 :: FPM

valB                            = 2.0 :: FPM -- doesn't work
-- valB                         = 2 :: FPM -- works


-- loopBug :: FPM -> (FPM,FPM)
loopBug valA                    = (o1, o2)
    where
        (o1,o2)         | valA < 0 = (-valC, valA+valB)
                        -- | otherwise = (valC, ((-valB)+valA))   -- works        
                        | otherwise = (valC, (valA-valB))       -- doesn't work


topEntity = loopBug

Throws CLaSH into a loop due to a bug in the DEC transformation.

@christiaanb christiaanb added the bug label Apr 4, 2016

christiaanb added a commit that referenced this issue Sep 6, 2018

Prelude changes to map `Bit` to a HDL scalar type (#140)
So instead of mapping `Bit` to

VHDL: `std_logic_vector(0 downto 0)`
Verilog: `wire [0:0]`

We map `Bit` to:

VHDL: `std_logic`
Verilog: `wire`

christiaanb added a commit that referenced this issue Sep 6, 2018

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