Allow annotation/attributes on modules (verilog) / architectures (vhdl)

[christiaanb]

Quartus allows you to set synthesis attributes on

• Modules: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_attribute.htm
• Architectures: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vhdl/vhdl_file_dir_attribute.htm

Similarly on Vivado:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug901-vivado-synthesis.pdf#page=41

I think the best place to add this information is in the Synthesize annotation:

clash-compiler/clash-prelude/src/Clash/Annotations/TopEntity.hs

Lines 224 to 240 in b574a92

	-- | TopEntity annotation
	data TopEntity
	-- | Instruct the Clash compiler to use this top-level function as a separately
	-- synthesizable component.
	= Synthesize
	{ t_name :: String
	-- ^ The name the top-level component should have, put in a correspondingly
	-- named file.
	, t_inputs :: [PortName]
	-- ^ List of names that are assigned in-order to the inputs of the component.
	, t_output :: PortName
	-- ^ Name assigned in-order to the outputs of the component. As a Haskell
	-- function can only truly return a single value -- with multiple values
	-- \"wrapped\" by a tuple -- this field is not a list, but a single
	-- @'PortName'@. Use @'PortProduct'@ to give names to the individual components
	-- of the output tuple.
	}

[hcab14]

Would this include the possibility to add annotations toInstDecl?

The use case is the ECP5 EXHPLL intrinsic, see below.

I know this can be done using an InlinePrimitve annotation. However to generate bindings to all variations of such PLLs it would be better to generate the Clash AST using a template function and for that it would be useful to have annotations for InstDecl.

Verilog code to be generated:

(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
EHXPLLL #(
        .PLLRST_ENA("ENABLED"),
        .INTFB_WAKE("DISABLED"),
        .STDBY_ENABLE("DISABLED"),
        .DPHASE_SOURCE("DISABLED"),
        .OUTDIVIDER_MUXA("DIVA"),
        .OUTDIVIDER_MUXB("DIVB"),
        .OUTDIVIDER_MUXC("DIVC"),
        .OUTDIVIDER_MUXD("DIVD"),
        .CLKI_DIV(3),
        .CLKOP_ENABLE("ENABLED"),
        .CLKOP_DIV(1),
        .CLKOP_CPHASE(0),
        .CLKOP_FPHASE(0),
        .FEEDBK_PATH("CLKOP"),
        .CLKFB_DIV(25)
    ) pll_i (
        .RST(reset),
        .STDBY(1'b0),
        .CLKI(clkin),
        .CLKOP(clkout0),
        .CLKFB(clkout0),
        .CLKINTFB(),
        .PHASESEL0(1'b0),
        .PHASESEL1(1'b0),
        .PHASEDIR(1'b1),
        .PHASESTEP(1'b1),
        .PHASELOADREG(1'b1),
        .PLLWAKESYNC(1'b0),
        .ENCLKOP(1'b0),
        .LOCK(locked)
        );