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dataMem :: Signal MemAddr -- ^ Read address
-> Signal MemAddr -- ^ Write address
-> Signal Bool -- ^ Write enable
-> Signal Value -- ^ data in
-> Signal Value -- ^ data out
dataMem wr rd en din = mealy dataMemT (replicate d32 0) (bundle (wr,rd,en,din))
where
dataMemT mem (wr,rd,en,din) = (mem',dout)
where
dout = mem !! rd
mem' | en = replace wr din mem
| otherwise = mem
It seems to me that the first argument to dataMem should be rd instead of wr, is that right? My guess is that since, in the next section of code that calls dataMem, the call swaps those args too, so it works as expected.
memOut = dataMem wrAddr rdAddr wrEn aluOut
Am I missing something?
The text was updated successfully, but these errors were encountered:
No... you're not missing anything... The haddock comments accompanying the function are swapped. The first argument is the write address, and the second argument is the read address.
For those thinking, "isn't it somewhat arrogant to write a Hedgehog test
for Euclid's third axiom?", rest assured I accidentally mixed up `c` and
`b` and only found out thanks to the test.
From this page, in the first
cpu
example:It seems to me that the first argument to dataMem should be
rd
instead ofwr
, is that right? My guess is that since, in the next section of code that calls dataMem, the call swaps those args too, so it works as expected.Am I missing something?
The text was updated successfully, but these errors were encountered: