VHDL generation error: wrapper for sum-of-products type

[DigitalBrains1]

When wrapping a sum-of-products type in a single-field record type, the generated VHDL is wrong; it seems to me like a superfluous VHDL signal is generated that has the type of the sum-of-products type (equivalently, the record type), but is used both that way and as if it where the product term in one of the sum constructors:

  port(w_i1     : in std_logic_vector(29 downto 0);
[...]
  signal repANF_0 : std_logic_vector(29 downto 0);
  signal repANF_1 : unsigned(3 downto 0);
  signal n_6      : unsigned(3 downto 0);
  signal ww1_8    : std_logic_vector(29 downto 0);
[...]
 repANF_0 <= ww1_8;

  repANF_1 <= n_6 + to_unsigned(1,4);

  n_6 <= unsigned(ww1_8(27 downto 24));

  ww1_8 <= unsigned(w_i1(27 downto 24));

Where it seems to me it should be this:

[...]
  signal repANF_0 : std_logic_vector(29 downto 0);
  signal repANF_1 : unsigned(3 downto 0);
  signal n_6      : unsigned(3 downto 0);
[...]
  repANF_0 <= w_i1;

  repANF_1 <= n_6 + to_unsigned(1,4);

  n_6 <= unsigned(w_i1(27 downto 24));

Obviously, if it were used correctly, it wouldn't matter that the signal is superfluous. But right now it is trying to be two things at once.

The VHDL generated above is generated by CλaSH v0.4.1 with Prelude v0.6.1 for the following CλaSH code:

{-# LANGUAGE DataKinds #-}
{-# LANGUAGE TemplateHaskell #-}

module RecordSumOfProducts where

import CLaSH.Prelude
import Control.Applicative

data DbState = DbInitDisp (Unsigned 4) | DbWriteRam (Signed 14) (Signed 14)
             | DbDone
    deriving (Show, Eq)

data DbS = DbS { dbS :: DbState }


topEntity = walkState <^> DbS (DbInitDisp 0)

walkState :: DbS
          -> Bit
          -> (DbS, Bit)

walkState (DbS (DbInitDisp n    )) i = (DbS (DbInitDisp (n+1)  ), 0)
walkState s                        i = (s                       , i)