Port name clashes with signal name

[gergoerdi]

CLaSH version: 949a05a

The following CLaSH source code produces no scoping errors from clash:

import Clash.Prelude

{-# NOINLINE topEntity #-}
{-# ANN topEntity
  (Synthesize
    { t_name   = "Bug"
    , t_inputs =
          [ PortName "CLK_50MHZ"
          , PortName "RESET"
          ]
    , t_output = PortName "LED"
    }) #-}
topEntity
    :: Clock System Source
    -> Reset System Asynchronous
    -> Signal System Bit
topEntity = exposeClockReset board
  where
    board = boolToBit <$> led
    led = register True $ complement <$> led

However, the VHDL generated from it has a name clash between the port name LED and the code generated for the locally bound variable led.

[gergoerdi]

Yes, ha ha, name clash, let's get this out of the way quickly :)