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topEntity = low
Main.topEntity8214565720323842134 after normalization: letrec result0 :: Bit = BitVector.low in (result0 :: Bit)
VHDL:
result <= '0';
Verilog:
assign \#i = 64'sd0; assign \#i_0 = 64'sd0; assign result = 1'b0;
SystemVerilog:
assign result = 1'b0;
topEntity = complement high
Main.topEntity8214565720323842134 after normalization: letrec result0 :: Bit = BitVector.fromInteger## 0 (-2) in (result0 :: Bit)
\#i_0\ <= to_signed(0,64); \#i\ <= to_signed(-2,64); result <= \#i\(0) when '0' = \#i_0\(0) else '-';
assign \#i = 64'sd0; assign \#i_0 = -64'sd2; assign result = 1'b0;
The text was updated successfully, but these errors were encountered:
Don't leak Bit(Vector) impl details in gen HDL
c1e28f1
Fixes #500
Don't leak Bit(Vector) impl details in gen HDL (#506)
3422987
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topEntity = low
VHDL:
Verilog:
SystemVerilog:
topEntity = complement high
VHDL:
Verilog:
SystemVerilog:
The text was updated successfully, but these errors were encountered: