Maybe (Index n) not translatable to VHDL

[leonschoorl]

When trying to translate something containing the type Maybe (Index n) to VHDL the compiler dies with:

CLaSH.Backend.VHDL(619): toSLV: ty:Index 8
 expr: Identifier "repANF_0" Nothing

Translating to (System)Verilog works without problems.

I have distilled it down to a simple test case:

module TestIndex where
import CLaSH.Prelude

type NrI = Index 8
type NrU = Unsigned 3

topEntity = c1

-- crashes
c1 :: Signal (Maybe NrI) -> Signal (Maybe NrI)
c1 = fmap (fmap (+1))

-- but this works fine
c2 :: Signal (Maybe NrU) -> Signal (Maybe NrU)
c2 = fmap (fmap (+1))

-- and this also works
c3 :: Signal NrI -> Signal NrI
c3 = fmap (+1)

[christiaanb]

Seems that a line like:

toSLV (Index _) e = "std_logic_vector" <> parens (expr_ False e)

is missing from https://github.com/clash-lang/clash-compiler/blob/master/clash-vhdl/src/CLaSH/Backend/VHDL.hs#L596