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Naming registers disconnects their output #967

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leonschoorl opened this issue Dec 13, 2019 · 3 comments · Fixed by #989
Closed

Naming registers disconnects their output #967

leonschoorl opened this issue Dec 13, 2019 · 3 comments · Fixed by #989
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@leonschoorl
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topEntity x = setName @"myRegister" $ register @System (0::Int) x
entity topentity is
  port(-- clock
       \$dIP\  : in main_types.clk_system;
       \$dIP1\ : in boolean;
       -- reset
       \$dIP2\ : in main_types.rst_system;
       eta     : in signed(63 downto 0);
       result  : out signed(63 downto 0));
end;

architecture structural of topentity is
begin
  -- register begin 
  myregister_register : process(\$dIP\,\$dIP2\)
  begin
    if \$dIP2\ =  '1'  then
      myRegister <= to_signed(0,64);
    elsif rising_edge(\$dIP\) then
      if \$dIP1\ then
        myRegister <= eta;
      end if;
    end if;
  end process;
  -- register end
end;

The register blackbox uses the name myRegister, but there's no signal declared with this name.
Nor is it connected to the result out port.

And delay has the same issue.

@christiaanb
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Right... the special blackbox result Name handling code, used by register and delay, doesn’t seem to deal with the context where the result is the output of the entity.

@leonschoorl
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Also the powerup value isn't rendered in HDL.
But that probably has the same cause.

@christiaanb
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christiaanb commented Dec 16, 2019

#781 is the PR added the "primitive-can-control-result-naming" code, specifically 048c46a

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3 participants