New unsafeSimSynchronizer, use in outputVerifier #1931
Merged
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Warn when
Clash.Explicit.Testbench.outputVerifier
is used in HDL whichis not marked as being a test bench and is given different clock domains
as
testDom
andcircuitDom
. IftestDom
andcircuitDom
refer tothe same domain, the warning is not emitted.
To this purpose, a new primitive
unsafeSimSynchronizer
is added toClash.Explicit.Testbench
, and it is used if a clock domain crossing isneeded in
outputVerifier
.The code for
outputVerifier
is also cleaned up. It now declares itneeds a non-empty list of samples to verify, since it never worked with
an empty list. Common code is split off and shared rather than
duplicated, and it now uses
Bounded
andSaturatingNum
to work withthe
Index
iterating the samples instead of writing out the samefunctionality.
Rationale:
outputVerifier
does clock domain crossing in a manner thatis not suitable for actual hardware but is efficient for HDL simulation.
The code was not intended to be used outside of a test bench context,
but nonetheless it could be synthesized as part of hardware. If a
user does this, we should warn them that the resulting hardware is
improper.
The user can then add their own clock domain crossing in the circuit if
they would need this functionality. An imaginable use of
outputVerifier
in a circuit is in combination with an ILA standing infor the
assert
behavior.Still TODO: