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Disallow implicit nets in (System)Verilog #2174

Merged

alex-mckenna merged 1 commit into master from no-default-nettype

Apr 21, 2022

Contributor

alex-mckenna commented Apr 21, 2022 •

edited

Verilog allows nets to be implicitly defined in a module, assuming
they are of type wire by default. However, for Clash-generated
Verilog it should never be the case that a net is implicitly defined
in a design. We can disallow this by setting the default net type
to none.

According to IEEE 1364-2005:

When the `default_nettype is set to none, all nets shall be
explicitly declared. If a net is not explicitly declared,
an error is generated.

This seems a much more sensible default for Clash.

Still TODO:

Write a changelog entry (see changelog/README.md)
Check copyright notices are up to date in edited files


          Disallow implicit nets in (System)Verilog

f21762f

Verilog allows nets to be implicitly defined in a module, assuming
they are of type `wire` by default. However, for Clash-generated
Verilog it should never be the case that a net is implicitly defined
in a design. We can disallow this by setting the default net type
to none.

According to IEEE 1364-2005:

    When the `default_nettype is set to none, all nets shall be
    explicitly declared. If a net is not explicitly declared,
    an error is generated.

This seems a much more sensible default for Clash.

alex-mckenna requested a review from martijnbastiaan

April 21, 2022 09:25

martijnbastiaan approved these changes

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martijnbastiaan left a comment

Agreed, this seems much more sensible.

alex-mckenna enabled auto-merge (squash)

April 21, 2022 09:30

alex-mckenna merged commit 753f583 into master

alex-mckenna deleted the no-default-nettype branch

April 21, 2022 10:10

martijnbastiaan added a commit that referenced this pull request


          Revert "Disallow implicit nets in (System)Verilog (#2174)"

4370a42

This reverts commit 753f583.

martijnbastiaan added a commit that referenced this pull request


          Revert "Disallow implicit nets in (System)Verilog (#2174)"

82a7477

This reverts commit 753f583.

vmchale pushed a commit that referenced this pull request


          Revert "Disallow implicit nets in (System)Verilog (#2174)"

cd15f4f

This reverts commit 753f583.

vmchale added a commit that referenced this pull request


          Revert "Revert "Disallow implicit nets in (System)Verilog (#2174)""

1606c63

This reverts commit cd15f4f.

allow implicit nets in (System)Verilog again

vmchale pushed a commit that referenced this pull request


          Revert "Disallow implicit nets in (System)Verilog (#2174)"

2d38fba

This reverts commit 753f583.

vmchale added a commit that referenced this pull request


          Revert "Revert "Disallow implicit nets in (System)Verilog (#2174)""

c830cd9

This reverts commit cd15f4f.

allow implicit nets in (System)Verilog again

vmchale pushed a commit that referenced this pull request


          Revert "Disallow implicit nets in (System)Verilog (#2174)"

4fcfcdd

This reverts commit 753f583.

vmchale added a commit that referenced this pull request


          Revert "Revert "Disallow implicit nets in (System)Verilog (#2174)""

7f63969

This reverts commit cd15f4f.

allow implicit nets in (System)Verilog again

vmchale pushed a commit that referenced this pull request


          Revert "Disallow implicit nets in (System)Verilog (#2174)"

7db9618

This reverts commit 753f583.

vmchale added a commit that referenced this pull request


          Revert "Revert "Disallow implicit nets in (System)Verilog (#2174)""

212728e

This reverts commit cd15f4f.

allow implicit nets in (System)Verilog again

alex-mckenna pushed a commit that referenced this pull request


          Always include the net type wire in (System)Verilog

daf7151

When declaring input ports / inout ports, the net type still has
to be specified as there are multiple valid net types (it just so
happens that Clash only cares about producing wires). This fixes
an unintended mistake introduced in #2174.

alex-mckenna mentioned this pull request

Always include the net type wire in (System)Verilog #2239

Merged

2 tasks

leonschoorl pushed a commit that referenced this pull request


          Always include the net type wire in (System)Verilog (#2239)

5968d8d

When declaring input ports / inout ports, the net type still has
to be specified as there are multiple valid net types (it just so
happens that Clash only cares about producing wires). This fixes
an unintended mistake introduced in #2174.

vmchale pushed a commit that referenced this pull request


          Revert "Disallow implicit nets in (System)Verilog (#2174)"

06a9744

This reverts commit 753f583.

vmchale added a commit that referenced this pull request


          Revert "Revert "Disallow implicit nets in (System)Verilog (#2174)""

433697b

This reverts commit cd15f4f.

allow implicit nets in (System)Verilog again

vmchale pushed a commit that referenced this pull request


          Revert "Disallow implicit nets in (System)Verilog (#2174)"

f882b86

This reverts commit 753f583.

vmchale added a commit that referenced this pull request


          Revert "Revert "Disallow implicit nets in (System)Verilog (#2174)""

4b707a4

This reverts commit cd15f4f.

allow implicit nets in (System)Verilog again

vmchale pushed a commit that referenced this pull request


          Revert "Disallow implicit nets in (System)Verilog (#2174)"

ccd7d7d

This reverts commit 753f583.

vmchale added a commit that referenced this pull request


          Revert "Revert "Disallow implicit nets in (System)Verilog (#2174)""

d54d6d8

This reverts commit cd15f4f.

allow implicit nets in (System)Verilog again

vmchale pushed a commit that referenced this pull request


          Revert "Disallow implicit nets in (System)Verilog (#2174)"

3f95abe

This reverts commit 753f583.

vmchale added a commit that referenced this pull request


          Revert "Revert "Disallow implicit nets in (System)Verilog (#2174)""

2ba0e8f

This reverts commit cd15f4f.

allow implicit nets in (System)Verilog again

vmchale pushed a commit that referenced this pull request


          Revert "Disallow implicit nets in (System)Verilog (#2174)"

e0cf530

This reverts commit 753f583.

vmchale added a commit that referenced this pull request


          Revert "Revert "Disallow implicit nets in (System)Verilog (#2174)""

1dd45b2

This reverts commit cd15f4f.

allow implicit nets in (System)Verilog again

vmchale pushed a commit that referenced this pull request


          Revert "Disallow implicit nets in (System)Verilog (#2174)"

fa3eea7

This reverts commit 753f583.

vmchale added a commit that referenced this pull request


          Revert "Revert "Disallow implicit nets in (System)Verilog (#2174)""

74d2040

This reverts commit cd15f4f.

allow implicit nets in (System)Verilog again

vmchale pushed a commit that referenced this pull request


          Revert "Disallow implicit nets in (System)Verilog (#2174)"

30b90ab

This reverts commit 753f583.

vmchale added a commit that referenced this pull request


          Revert "Revert "Disallow implicit nets in (System)Verilog (#2174)""

850f4a2

This reverts commit cd15f4f.

allow implicit nets in (System)Verilog again

vmchale pushed a commit that referenced this pull request


          Revert "Disallow implicit nets in (System)Verilog (#2174)"

b4ecf88

This reverts commit 753f583.

vmchale added a commit that referenced this pull request


          Revert "Revert "Disallow implicit nets in (System)Verilog (#2174)""

05e2c3b

This reverts commit cd15f4f.

allow implicit nets in (System)Verilog again

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