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trueDualPortBlockRam# cleanup #2433

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merged 3 commits into from
Mar 15, 2023
Merged

trueDualPortBlockRam# cleanup #2433

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18cb48d
Move `trueDualPortBlockRam#` blackboxes to inline YAML
martijnbastiaan Mar 2, 2023
e80b475
Use named symbols in `trueDualPortBlockRam#` blackboxes
martijnbastiaan Mar 2, 2023
0cda2e8
Remove domain ordering from 'trueDualPortBlockRam'
martijnbastiaan Feb 10, 2023
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3 changes: 3 additions & 0 deletions .gitignore
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Expand Up @@ -59,3 +59,6 @@ docs/env

# rewrite histories
*.dat

# build_clash_dev.sh output
clash-dev.result
57 changes: 0 additions & 57 deletions clash-lib/prims/systemverilog/Clash_Explicit_BlockRam.primitives.yaml
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Expand Up @@ -131,60 +131,3 @@
end~FI
assign ~RESULT = ~FROMBV[~SYM[2]][~TYP[10]];
// blockRam1 end
- BlackBox:
name: Clash.Explicit.BlockRam.trueDualPortBlockRam#
kind: Declaration
type: |-
trueDualPortBlockRam# ::
forall nAddrs domA domB a .
( HasCallStack ~ARG[0]
, KnownNat nAddrs ~ARG[1]
, KnownDomain domA ~ARG[2]
, KnownDomain domB ~ARG[3]
, NFDataX a ~ARG[4]
) =>

Clock domA -> ~ARG[5]
Signal domA Bool -> ~ARG[6]
Signal domA Bool -> ~ARG[7]
Signal domA (Index nAddrs) -> ~ARG[8]
Signal domA a -> ~ARG[9]

Clock domB -> ~ARG[10]
Signal domB Bool -> ~ARG[11]
Signal domB Bool -> ~ARG[12]
Signal domB (Index nAddrs) -> ~ARG[13]
Signal domB a -> ~ARG[14]
(Signal domA a, Signal domB a)
template: |-
// trueDualPortBlockRam begin
// Shared memory
logic [~SIZE[~TYP[9]]-1:0] ~GENSYM[mem][0] [~LIT[1]-1:0];

~SIGD[~GENSYM[data_slow][1]][9];
~SIGD[~GENSYM[data_fast][2]][14];

// Port A
always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[5]) begin
if(~ARG[6]) begin
~SYM[1] <= ~SYM[0][~IF~SIZE[~TYP[8]]~THEN~ARG[8]~ELSE0~FI];
if(~ARG[7]) begin
~SYM[1] <= ~ARG[9];
~SYM[0][~IF~SIZE[~TYP[8]]~THEN~ARG[8]~ELSE0~FI] <= ~ARG[9];
end
end
end

// Port B
always @(~IF~ACTIVEEDGE[Rising][3]~THENposedge~ELSEnegedge~FI ~ARG[10]) begin
if(~ARG[11]) begin
~SYM[2] <= ~SYM[0][~IF~SIZE[~TYP[13]]~THEN~ARG[13]~ELSE0~FI];
if(~ARG[12]) begin
~SYM[2] <= ~ARG[14];
~SYM[0][~IF~SIZE[~TYP[13]]~THEN~ARG[13]~ELSE0~FI] <= ~ARG[14];
end
end
end

assign ~RESULT = {~SYM[1], ~SYM[2]};
// end trueDualPortBlockRam
58 changes: 0 additions & 58 deletions clash-lib/prims/verilog/Clash_Explicit_BlockRam.primitives.yaml
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Expand Up @@ -142,61 +142,3 @@
~RESULT <= ~SYM[0][~ARG[7]];
end~FI
// blockRam1 end
- BlackBox:
name: Clash.Explicit.BlockRam.trueDualPortBlockRam#
kind: Declaration
type: |-
trueDualPortBlockRam# ::
forall nAddrs domA domB a .
( HasCallStack ~ARG[0]
, KnownNat nAddrs ~ARG[1]
, KnownDomain domA ~ARG[2]
, KnownDomain domB ~ARG[3]
, NFDataX a ~ARG[4]
) =>

Clock domA -> ~ARG[5]
Signal domA Bool -> ~ARG[6]
Signal domA Bool -> ~ARG[7]
Signal domA (Index nAddrs) -> ~ARG[8]
Signal domA a -> ~ARG[9]

Clock domB -> ~ARG[10]
Signal domB Bool -> ~ARG[11]
Signal domB Bool -> ~ARG[12]
Signal domB (Index nAddrs) -> ~ARG[13]
Signal domB a -> ~ARG[14]
(Signal domA a, Signal domB a)
template: |-
// trueDualPortBlockRam begin
// Shared memory
reg [~SIZE[~TYP[9]]-1:0] ~GENSYM[mem][0] [~LIT[1]-1:0];

reg ~SIGD[~GENSYM[data_slow][1]][9];
reg ~SIGD[~GENSYM[data_fast][2]][14];

// Port A
always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[5]) begin
if(~ARG[6]) begin
~SYM[1] <= ~SYM[0][~IF~SIZE[~TYP[8]]~THEN~ARG[8]~ELSE0~FI];
if(~ARG[7]) begin
~SYM[1] <= ~ARG[9];
~SYM[0][~IF~SIZE[~TYP[8]]~THEN~ARG[8]~ELSE0~FI] <= ~ARG[9];
end
end
end

// Port B
always @(~IF~ACTIVEEDGE[Rising][3]~THENposedge~ELSEnegedge~FI ~ARG[10]) begin
if(~ARG[11]) begin
~SYM[2] <= ~SYM[0][~IF~SIZE[~TYP[13]]~THEN~ARG[13]~ELSE0~FI];
if(~ARG[12]) begin
~SYM[2] <= ~ARG[14];
~SYM[0][~IF~SIZE[~TYP[13]]~THEN~ARG[13]~ELSE0~FI] <= ~ARG[14];
end
end
end

assign ~RESULT = {~SYM[1], ~SYM[2]};

// end trueDualPortBlockRam
64 changes: 0 additions & 64 deletions clash-lib/prims/vhdl/Clash_Explicit_BlockRam.primitives.yaml
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Expand Up @@ -171,67 +171,3 @@
end process; ~FI
end block;
--end blockRam1
- BlackBox:
name: Clash.Explicit.BlockRam.trueDualPortBlockRam#
kind: Declaration
type: |-
trueDualPortBlockRam# ::
forall nAddrs domA domB a .
( HasCallStack ~ARG[0]
, KnownNat nAddrs ~ARG[1]
, KnownDomain domA ~ARG[2]
, KnownDomain domB ~ARG[3]
, NFDataX a ~ARG[4]
) =>

Clock domA -> ~ARG[5]
Signal domA Bool -> ~ARG[6]
Signal domA Bool -> ~ARG[7]
Signal domA (Index nAddrs) -> ~ARG[8]
Signal domA a -> ~ARG[9]

Clock domB -> ~ARG[10]
Signal domB Bool -> ~ARG[11]
Signal domB Bool -> ~ARG[12]
Signal domB (Index nAddrs) -> ~ARG[13]
Signal domB a -> ~ARG[14]
(Signal domA a, Signal domB a)
template: |-
-- trueDualPortBlockRam begin
~GENSYM[~RESULT_trueDualPortBlockRam][1] : block
-- Shared memory
type mem_type is array ( ~LIT[1]-1 downto 0 ) of ~TYP[9];
shared variable mem : mem_type;
signal ~GENSYM[a_dout][2] : ~TYP[9];
signal ~GENSYM[b_dout][3] : ~TYP[14];
begin

-- Port A
process(~ARG[5])
begin
if(rising_edge(~ARG[5])) then
if(~ARG[6]) then
if(~ARG[7]) then
mem(~IF~SIZE[~TYP[8]]~THENto_integer(~ARG[8])~ELSE0~FI) := ~ARG[9];
end if;
~SYM[2] <= mem(~IF~SIZE[~TYP[8]]~THENto_integer(~ARG[8])~ELSE0~FI);
end if;
end if;
end process;

-- Port B
process(~ARG[10])
begin
if(rising_edge(~ARG[10])) then
if(~ARG[11]) then
if(~ARG[12]) then
mem(~IF~SIZE[~TYP[13]]~THENto_integer(~ARG[13])~ELSE0~FI) := ~ARG[14];
end if;
~SYM[3] <= mem(~IF~SIZE[~TYP[13]]~THENto_integer(~ARG[13])~ELSE0~FI);
end if;
end if;
end process;

~RESULT <= (~SYM[2], ~SYM[3]);
end block;
-- end trueDualPortBlockRam
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