clash-lang · martijnbastiaan · Mar 6, 2019 · Mar 6, 2019
diff --git a/clash-ghc/clash-ghc.cabal b/clash-ghc/clash-ghc.cabal
@@ -2,12 +2,12 @@ Name:                 clash-ghc
 Version:              0.99
 Synopsis:             CAES Language for Synchronous Hardware
 Description:
-  CλaSH (pronounced ‘clash’) is a functional hardware description language that
-  borrows both its syntax and semantics from the functional programming language
-  Haskell. The CλaSH compiler transforms these high-level descriptions to
-  low-level synthesizable VHDL, Verilog, or SystemVerilog.
+  Clash is a functional hardware description language that borrows both its
+  syntax and semantics from the functional programming language Haskell. The
+  Clash compiler transforms these high-level descriptions to low-level
+  synthesizable VHDL, Verilog, or SystemVerilog.
   .
-  Features of CλaSH:
+  Features of Clash:
   .
   * Strongly typed, but with a very high degree of type inference, enabling both
     safe and fast prototyping using concise descriptions.
@@ -26,7 +26,7 @@ Description:
   .
   This package provides:
   .
-  * CλaSH Compiler binary using GHC/Haskell as a frontend
+  * Clash Compiler binary using GHC/Haskell as a frontend
   .
   .
   Prelude library: <http://hackage.haskell.org/package/clash-prelude>

diff --git a/clash-lib/clash-lib.cabal b/clash-lib/clash-lib.cabal
@@ -2,12 +2,12 @@ Name:                 clash-lib
 Version:              0.99
 Synopsis:             CAES Language for Synchronous Hardware - As a Library
 Description:
-  CλaSH (pronounced ‘clash’) is a functional hardware description language that
-  borrows both its syntax and semantics from the functional programming language
-  Haskell. The CλaSH compiler transforms these high-level descriptions to
-  low-level synthesizable VHDL, Verilog, or SystemVerilog.
+  Clash is a functional hardware description language that borrows both its
+  syntax and semantics from the functional programming language Haskell. The
+  Clash compiler transforms these high-level descriptions to low-level
+  synthesizable VHDL, Verilog, or SystemVerilog.
   .
-  Features of CλaSH:
+  Features of Clash:
   .
   * Strongly typed, but with a very high degree of type inference, enabling both
     safe and fast prototyping using concise descriptions.

diff --git a/clash-prelude/clash-prelude.cabal b/clash-prelude/clash-prelude.cabal
@@ -2,12 +2,12 @@ Name:                 clash-prelude
 Version:              0.99
 Synopsis:             CAES Language for Synchronous Hardware - Prelude library
 Description:
-  CλaSH (pronounced ‘clash’) is a functional hardware description language that
-  borrows both its syntax and semantics from the functional programming language
-  Haskell. The CλaSH compiler transforms these high-level descriptions to
-  low-level synthesizable VHDL, Verilog, or SystemVerilog.
+  Clash is a functional hardware description language that borrows both its
+  syntax and semantics from the functional programming language Haskell. The
+  Clash compiler transforms these high-level descriptions to low-level
+  synthesizable VHDL, Verilog, or SystemVerilog.
   .
-  Features of CλaSH:
+  Features of Clash:
   .
   * Strongly typed, but with a very high degree of type inference, enabling both
     safe and fast prototyping using concise descriptions.

diff --git a/clash-prelude/src/Clash/Annotations/TopEntity.hs b/clash-prelude/src/Clash/Annotations/TopEntity.hs
@@ -5,7 +5,7 @@ License    :  BSD2 (see the file LICENSE)
 Maintainer :  Christiaan Baaij <christiaan.baaij@gmail.com>
 
 'TopEntity' annotations allow us to control hierarchy and naming aspects of the
-CλaSH compiler. We have the 'Synthesize' and 'TestBench' annotation.
+Clash compiler. We have the 'Synthesize' and 'TestBench' annotation.
 
 === 'Synthesize' annotation
 
@@ -32,7 +32,7 @@ restrictions:
 
 Also take the following into account when using 'Synthesize' annotations.
 
-    * The CλaSH compiler is based on the GHC Haskell compiler, and the GHC
+    * The Clash compiler is based on the GHC Haskell compiler, and the GHC
       machinery does not understand 'Synthesize' annotations and it might
       subsequently decide to inline those functions. You should therefor also
       add a @{\-\# NOINLINE f \#-\}@ pragma to the functions which you give
@@ -41,7 +41,7 @@ Also take the following into account when using 'Synthesize' annotations.
       on constants.
 
 Finally, the root module, the module which you pass as an argument to the
-CλaSH compiler must either have:
+Clash compiler must either have:
 
     * A function with a 'Synthesize' annotation.
     * A function called /topEntity/.
@@ -93,7 +93,7 @@ blinkerT (leds,mode,cntr) key1R = ((leds',mode',cntr'),leds)
           | otherwise = leds
 @
 
-The CλaSH compiler would normally generate the following
+The Clash compiler would normally generate the following
 @blinker_topentity.vhdl@ file:
 
 @
@@ -139,7 +139,7 @@ However, if we add the following 'Synthesize' annotation in the file:
     }) \#-\}
 @
 
-The CλaSH compiler will generate the following @blinker.vhdl@ file instead:
+The Clash compiler will generate the following @blinker.vhdl@ file instead:
 
 @
 -- Automatically generated VHDL-93

diff --git a/clash-prelude/src/Clash/Explicit/BlockRam.hs b/clash-prelude/src/Clash/Explicit/BlockRam.hs
@@ -12,7 +12,7 @@ BlockRAM primitives
 We will show a rather elaborate example on how you can, and why you might want
 to use 'blockRam's. We will build a \"small\" CPU+Memory+Program ROM where we
 will slowly evolve to using blockRams. Note that the code is /not/ meant as a
-de-facto standard on how to do CPU design in CλaSH.
+de-facto standard on how to do CPU design in Clash.
 
 We start with the definition of the Instructions, Register names and machine
 codes:

diff --git a/clash-prelude/src/Clash/Explicit/Signal.hs b/clash-prelude/src/Clash/Explicit/Signal.hs
@@ -5,7 +5,7 @@ Copyright  :  (C) 2013-2016, University of Twente,
 License    :  BSD2 (see the file LICENSE)
 Maintainer :  Christiaan Baaij <christiaan.baaij@gmail.com>
 
-CλaSH has synchronous 'Signal's in the form of:
+Clash has synchronous 'Signal's in the form of:
 
 @
 'Signal' (domain :: 'Domain') a

diff --git a/clash-prelude/src/Clash/Explicit/Testbench.hs b/clash-prelude/src/Clash/Explicit/Testbench.hs
@@ -109,7 +109,7 @@ assertBitVector clk _rst msg checked expected returned =
 
 
 -- | To be used as one of the functions to create the \"magical\" 'testInput'
--- value, which the CλaSH compiler looks for to create the stimulus generator
+-- value, which the Clash compiler looks for to create the stimulus generator
 -- for the generated VHDL testbench.
 --
 -- Example:
@@ -146,7 +146,7 @@ stimuliGenerator clk rst samples =
 {-# INLINABLE stimuliGenerator #-}
 
 -- | To be used as one of the functions to generate the \"magical\" 'expectedOutput'
--- function, which the CλaSH compiler looks for to create the signal verifier
+-- function, which the Clash compiler looks for to create the signal verifier
 -- for the generated VHDL testbench.
 --
 -- Example:

diff --git a/clash-prelude/src/Clash/Prelude.hs b/clash-prelude/src/Clash/Prelude.hs
@@ -4,12 +4,12 @@
   License     :  BSD2 (see the file LICENSE)
   Maintainer  :  Christiaan Baaij <christiaan.baaij@gmail.com>
 
-  CλaSH (pronounced ‘clash’) is a functional hardware description language that
-  borrows both its syntax and semantics from the functional programming language
-  Haskell. The merits of using a functional language to describe hardware comes
-  from the fact that combinational circuits can be directly modeled as
-  mathematical functions and that functional languages lend themselves very well
-  at describing and (de-)composing mathematical functions.
+  Clash is a functional hardware description language that borrows both its
+  syntax and semantics from the functional programming language Haskell. The
+  merits of using a functional language to describe hardware comes from the fact
+  that combinational circuits can be directly modeled as mathematical functions
+  and that functional languages lend themselves very well at describing and
+  (de-)composing mathematical functions.
 
   This package provides:
 

diff --git a/clash-prelude/src/Clash/Prelude/BlockRam.hs b/clash-prelude/src/Clash/Prelude/BlockRam.hs
@@ -12,7 +12,7 @@ BlockRAM primitives
 We will show a rather elaborate example on how you can, and why you might want
 to use 'blockRam's. We will build a \"small\" CPU+Memory+Program ROM where we
 will slowly evolve to using blockRams. Note that the code is /not/ meant as a
-de-facto standard on how to do CPU design in CλaSH.
+de-facto standard on how to do CPU design in Clash.
 
 We start with the definition of the Instructions, Register names and machine
 codes:

diff --git a/clash-prelude/src/Clash/Prelude/Safe.hs b/clash-prelude/src/Clash/Prelude/Safe.hs
@@ -6,12 +6,12 @@
 
   __This is the <https://downloads.haskell.org/~ghc/latest/docs/html/users_guide/safe_haskell.html Safe> API only of "Clash.Prelude"__
 
-  CλaSH (pronounced ‘clash’) is a functional hardware description language that
-  borrows both its syntax and semantics from the functional programming language
-  Haskell. The merits of using a functional language to describe hardware comes
-  from the fact that combinational circuits can be directly modeled as
-  mathematical functions and that functional languages lend themselves very well
-  at describing and (de-)composing mathematical functions.
+  Clash is a functional hardware description language that borrows both its
+  syntax and semantics from the functional programming language Haskell. The
+  merits of using a functional language to describe hardware comes from the fact
+  that combinational circuits can be directly modeled as mathematical functions
+  and that functional languages lend themselves very well at describing and
+  (de-)composing mathematical functions.
 
   This package provides:
 

diff --git a/clash-prelude/src/Clash/Prelude/Testbench.hs b/clash-prelude/src/Clash/Prelude/Testbench.hs
@@ -55,7 +55,7 @@ assert = hideClockReset E.assert
 {-# INLINE assert #-}
 
 -- | To be used as one of the functions to create the \"magical\" 'testInput'
--- value, which the CλaSH compiler looks for to create the stimulus generator
+-- value, which the Clash compiler looks for to create the stimulus generator
 -- for the generated VHDL testbench.
 --
 -- Example:
@@ -77,7 +77,7 @@ stimuliGenerator = hideClockReset E.stimuliGenerator
 {-# INLINE stimuliGenerator #-}
 
 -- | To be used as one of the functions to generate the \"magical\" 'expectedOutput'
--- function, which the CλaSH compiler looks for to create the signal verifier
+-- function, which the Clash compiler looks for to create the signal verifier
 -- for the generated VHDL testbench.
 --
 -- Example:

diff --git a/clash-prelude/src/Clash/Signal.hs b/clash-prelude/src/Clash/Signal.hs
@@ -5,7 +5,7 @@ Copyright  :  (C) 2013-2016, University of Twente,
 License    :  BSD2 (see the file LICENSE)
 Maintainer :  Christiaan Baaij <christiaan.baaij@gmail.com>
 
-CλaSH has synchronous 'Signal's in the form of:
+Clash has synchronous 'Signal's in the form of:
 
 @
 'Signal' (domain :: 'Domain') a

diff --git a/clash-prelude/src/Clash/Signal/Internal.hs b/clash-prelude/src/Clash/Signal/Internal.hs
@@ -125,7 +125,7 @@ data Domain = Dom { domainName :: Symbol, clkPeriod :: Nat }
   deriving (Typeable)
 
 infixr 5 :-
-{- | CλaSH has synchronous 'Signal's in the form of:
+{- | Clash has synchronous 'Signal's in the form of:
 
 @
 'Signal' (domain :: 'Domain') a