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Fix VHDL primitive for CLaSH.Sized.Internal.Signed.size# #72

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merged 2 commits into from Sep 5, 2015

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leonschoorl
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@christiaanb
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The verilog and systemverilog primitives seem similarly broken, could you include a fix in your pull request for those too?

@leonschoorl
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Here you go.

I thought I had check them, but must have forgotten.

christiaanb added a commit that referenced this pull request Sep 5, 2015
Fix VHDL primitive for CLaSH.Sized.Internal.Signed.size#
@christiaanb christiaanb merged commit 8798012 into clash-lang:master Sep 5, 2015
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Thanks for the patch

@leonschoorl leonschoorl deleted the fix-Signed.size branch November 6, 2015 11:59
leonschoorl pushed a commit that referenced this pull request Jul 31, 2023
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2 participants