Merge pull request #51 from cms-l1-globaltrigger/dev_v1.27.x

dev_v1.27.x merge

.github/workflows/pylint.yml

@@ -7,7 +7,7 @@ jobs:
     runs-on: ubuntu-latest
     strategy:
       matrix:
-        python-version: ["3.7", "3.8", "3.9"]
+        python-version: ["3.8", "3.9", "3.10", "3.11"]
     steps:
     - uses: actions/checkout@v2
     - name: Set up Python ${{ matrix.python-version }}

CHANGELOG.md

@@ -4,6 +4,22 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/)
 and this project adheres to [Semantic Versioning](http://semver.org/).
 
+## [v1.27.0] - 2024-05-28
+### Comment
+
+- implemention of calo comb trigger with more than 4 objects (with a given object number and one pt threshold only)
+
+### Added
+- source files:
+  - ../payload/gtl/calo_comp_multi_condition.vhd
+- simulation file:
+  - ../sim/scripts/templates/gtl_fdl_wrapper_tpl_questa.do
+  - ../sim/scripts/calo_comp_multi_condition_test.do
+  - ../sim/scripts/calo_comp_multi_condition_wave.do
+  - ../sim/testbench/calo_comp_multi_condition_tb.vhd
+- dep file:
+  - ../cfg/uGT_algo.dep
+
 ## [v1.26.0] - 2024-03-14
 ### Comment
 

README.md

@@ -25,13 +25,13 @@ files:
 
 | utm | TME | VHDL Producer |
 |:-:|:-:|:-:|
-| 0.11.2 | 0.15.3 | 2.14.2 |
+| 0.13.0 | 0.17.0 | 2.19.0 |
 
 Following dependencies exist for uGT firmware:
 
 | Repo | Tag |
 |:-:|:-:|
-| [MP7](https://gitlab.cern.ch/cms-l1-globaltrigger/mp7) | v3.2.2_Vivado2021+_ugt_v2
+| [MP7](https://gitlab.cern.ch/cms-l1-globaltrigger/mp7) | v3.2.2_Vivado2021+_ugt_v4
 | [IPBB](https://github.com/ipbus/ipbb) | dev/2023a
 | [IPB_FW](https://github.com/ipbus/ipbus-firmware) | v1.4
 
@@ -77,28 +77,28 @@ export MGLS_LICENSE_FILE=1234@license.server
 export UGT_GITLAB_USER_NAME=hbergaue
 export UGT_QUESTASIMLIBS_DIR=/opt/mentor
 export UGT_QUESTASIM_SIM_PATH=${MODELSIM_ROOT}
-export UGT_VIVADO_QUESTASIMLIBS_VERSION=2019.2
+export UGT_VIVADO_QUESTASIMLIBS_VERSION=2021.2
 export UGT_QUESTASIM_LIBS_PATH=${UGT_QUESTASIMLIBS_DIR}/questasimlibs_vivado_${UGT_VIVADO_QUESTASIMLIBS_VERSION}
-export UGT_BLK_MEM_GEN_VERSION_SIM=blk_mem_gen_v8_4_4
+export UGT_BLK_MEM_GEN_VERSION_SIM=blk_mem_gen_v8_4_5
 
 ## Synthesis (Vivado)
 export VIVADO_BASE_DIR=/opt/xilinx/Vivado
 export UGT_VIVADO_BASE_DIR=${VIVADO_BASE_DIR}
-export UGT_VIVADO_VERSION=2019.2
-export UGT_BLK_MEM_GEN_VERSION_SYNTH=blk_mem_gen_v8_4_4
+export UGT_VIVADO_VERSION=2021.2
+export UGT_BLK_MEM_GEN_VERSION_SYNTH=blk_mem_gen_v8_4_5
 source ${VIVADO_BASE_DIR}/${UGT_VIVADO_VERSION}/settings64.sh
 ```
 
 ## Simulation
 
 Simulation of VHDL module `gtl_fdl_wrapper.vhd` with Questa simulator for 6 ugt modules.
 
-* This is a description running script [run_simulation_questa.py](scripts/run_simulation_questa.py) for simulation.
+* This is a description running script simulation.py in [ugt-fwtools](https://github.com/cms-l1-globaltrigger/ugt-fwtools) with ugt-simulate for simulation.
 * If Questasim libraries for a certain Vivado version do not exist, they have to
-be created for the selected Questasim version with script [run_compile_simlib.py](scripts/run_compile_simlib.py):
+be created for the selected Questasim version with script [ugt-fwtools](https://github.com/cms-l1-globaltrigger/ugt-fwtools) with ugt-compile-simlib:
 ```bash
-python scripts/run_compile_simlib.py \
- --vivado <vivado_version (e.g. 2019.2)> \
+ugt-compile-simlib \
+ --vivado <vivado_version (e.g. 2021.2)> \
  --questasim <path to Questasim (e.g. /opt/mentor/10.7c/questasim)> \
  --output <output directory for generated libraries>
 ```
@@ -124,31 +124,22 @@ Run simulation using Questa.
 - MIF files (for mass over deltaR) are located in `mp7_ugt_legacy/firmware/sim`
 for simulation.
 
-Running script
-
-```bash
-python scripts/run_simulation_questa.py <xml_file> --tv <testvector_file> [--ignored]
-```
+Running script simulation.py in [ugt-fwtools](https://github.com/cms-l1-globaltrigger/ugt-fwtools) with ugt-simulate.
 
 *Note:* inspect for default values and other arguments
 
 ```bash
-python scripts/run_simulation_questa.py -h
-```
-
-Example 1
-
-```bash
-python scripts/run_simulation_questa.py https://raw.githubusercontent.com/cms-l1-globaltrigger/cms-l1-menu/master/2022/L1Menu_Collisions2022_v1_4_0-d1/xml/L1Menu_Collisions2022_v1_4_0-d1.xml \
- --tv https://raw.githubusercontent.com/cms-l1-globaltrigger/cms-l1-menu/master/2022/L1Menu_Collisions2022_v1_4_0-d1/testvectors/TestVector_L1Menu_Collisions2022_v1_4_0_ttbar.txt \
- --ignored
+cd ../ugt-fwtools
+python3 -m venv env
+. env/bin/activate
+ugt-simulate <xml_file> --tv <testvector_file> --ugttag <ugt tag or branch> [--mp7_repo_tag <MP7 repo tag - default is v3.2.2_Vivado2021+_ugt_v4>] [--ignored]
 ```
 
-Example 2
+Example 
 
 ```bash
-python scripts/run_simulation_questa.py ./cms-l1-menu/2022/L1Menu_Collisions2022_v1_4_0-d1/xml/L1Menu_Collisions2022_v1_4_0-d1.xml \
- --tv ./cms-l1-menu/2022/L1Menu_Collisions2022_v1_4_0-d1/testvectors/TestVector_L1Menu_Collisions2022_v1_4_0_ttbar.txt \
+ugt-simulate https://raw.githubusercontent.com/cms-l1-globaltrigger/cms-l1-menu/L1Menu_Collisions2024_v1_2_1-d1/2024/L1Menu_Collisions2024_v1_2_1-d1/xml/L1Menu_Collisions2024_v1_2_1-d1.xml \
+ --tv https://raw.githubusercontent.com/cms-l1-globaltrigger/cms-l1-menu/L1Menu_Collisions2024_v1_2_1-d1/2024/L1Menu_Collisions2024_v1_2_1-d1/testvectors/TestVector_L1Menu_Collisions2024_v1_2_1_ttBar.txt \
  --ignored
 ```
 
@@ -168,22 +159,22 @@ that you have your Xilinx Vivado licensing already setup for your enviroment.
   - added [ugt_strategy.tcl](firmware/ucf/ugt_strategy.tcl) for ugt specific strategy and inserted it into [top.dep](firmware/cfg/top.dep).
   - added [add_l1menu_blkmem_files.tcl](firmware/cfg/add_l1menu_blkmem_files.tcl) for adding L1Menu VHDL files and inserted it into [top.dep](firmware/cfg/top.dep).
 
-* Following scripts are available for firmware sythesis, checking used FPGA resources and packing firmware files:
-  - script [runIpbbSynth.py](scripts/runIpbbSynth.py) for IPBB synthesis (all 6 mp7_ugt modules).
-  - script [checkIpbbSynth.py](scripts/checkIpbbSynth.py) for checking used FPGA resources.
-  - script [fwpackerIpbb.py](scripts/fwpackerIpbb.py) for packing firmware files in a tar file.
+* Following scripts are available in [ugt_fwtools](https://github.com/cms-l1-globaltrigger/ugt-fwtools/ugt_fwtools) for firmware sythesis, checking used FPGA resources and packing firmware files:
+  - script synthesis.py for IPBB synthesis (all 6 mp7_ugt modules).
+  - script checksynth.py for checking used FPGA resources.
+  - script fwpacker.py for packing firmware files in a tar file.
 
 * The [MP7](https://gitlab.cern.ch/cms-cactus/firmware/mp7) firmware needs to be adapted for Global Trigger firmware.
-* A script [mp7patch.py](scripts/mp7patch.py) make this changes in the following MP7 files (tag v3.0.0):
-  - [area_constraints.tcl](https://gitlab.cern.ch/cms-cactus/firmware/mp7/-/blob/v3.0.0/boards/mp7/base_fw/common/firmware/ucf/area_constraints.tcl)
-  - [mp7_brd_decl.vhd](https://gitlab.cern.ch/cms-cactus/firmware/mp7/-/blob/v3.0.0/boards/mp7/base_fw/mp7xe_690/firmware/hdl/mp7_brd_decl.vhd)
-  - [mp7xe_690.vhd](https://gitlab.cern.ch/cms-cactus/firmware/mp7/-/blob/v3.0.0/boards/mp7/base_fw/mp7xe_690/firmware/hdl/mp7xe_690.vhd)
-* Additionally this script inserts L1A (port l1a) to [mp7_payload.vhd](firmware/hdl/mp7_payload.vhd)
-* In [run_simulation_questa.py](scripts/run_simulation_questa.py) and [runIpbbSynth.py](scripts/runIpbbSynth.py), [mp7patch.py](scripts/mp7patch.py) is implemented to patch files without using [MP7_for_uGT](https://gitlab.cern.ch/hbergaue/mp7) anymore.
+* A script makes this changes in the following MP7 files:
+  - [area_constraints.tcl](https://gitlab.cern.ch/cms-cactus/firmware/mp7/-/blob/v3.2.2_Vivado2021+_ugt_v4/boards/mp7/base_fw/common/firmware/ucf/area_constraints.tcl)
+  - [mp7_brd_decl.vhd](https://gitlab.cern.ch/cms-cactus/firmware/mp7/-/blob/v3.2.2_Vivado2021+_ugt_v4/boards/mp7/base_fw/mp7xe_690/firmware/hdl/mp7_brd_decl.vhd)
+  - [mp7xe_690.vhd](https://gitlab.cern.ch/cms-cactus/firmware/mp7/-/blob/v3.2.2_Vivado2021+_ugt_v4/boards/mp7/base_fw/mp7xe_690/firmware/hdl/mp7xe_690.vhd)
+* Additionally this script inserts L1A (port l1a) to [mp7_payload.vhd](firmware/hdl/mp7_payload.vhd).
+* This script is part of simulation and synthesis workflows (ugt-simulate, ugt-synthesize).
 
 ### Workflow
 
-Make sure to setup ypur local bash environment (see above).
+Make sure to setup your local bash environment (see above).
 
 Run kerberos for outside of CERN network.
 
@@ -193,44 +184,28 @@ kinit <username>@CERN.CH
 
 Run synthesis script (for all 6 modules).
 
-```bash
-python scripts/run_synth_ipbb.py <xml_file> \
- --ugturl <ugt_url_to_git_repo> \
- --ugt <ugt_tag_or_branch> \
- --build <build_version> \
- -p <working_dir>
-```
-
 *Note:* inspect default values for arguments using
 
 ```bash
-python scripts/run_synth_ipbb.py -h
-```
-
-Example 1
-
+cd ../ugt-fwtools
+python3 -m venv env
+. env/bin/activate
+ugt-synthesize <xml_file> --ugt <ugt tag or branch> --mp7tag <MP7 repo tag - default is v3.2.2_Vivado2021+_ugt_v4> --build <build_version> -p <working_dir>
 ```bash
-python scripts/run_synth_ipbb.py https://raw.githubusercontent.com/cms-l1-globaltrigger/cms-l1-menu/master/2022/L1Menu_Collisions2022_v1_4_0-d1/xml/L1Menu_Collisions2022_v1_4_0-d1.xml \
- --ugturl https://github.com/cms-l1-globaltrigger/mp7_ugt_legacy \
- --ugt master \
- --build 0x113d \
- -p ~/work_synth/production
-```
 
-Example 2
+Example
 
 ```bash
-python scripts/run_synth_ipbb.py ./cms-l1-menu/2022/L1Menu_Collisions2022_v1_4_0-d1/xml/L1Menu_Collisions2022_v1_4_0-d1.xml \
- --ugturl https://github.com/cms-l1-globaltrigger/mp7_ugt_legacy \
- --ugt master \
- --build 0x113d \
+ugt-synthesize https://raw.githubusercontent.com/cms-l1-globaltrigger/cms-l1-menu/L1Menu_Collisions2024_v1_2_1-d1/2024/L1Menu_Collisions2024_v1_2_1-d1/xml/L1Menu_Collisions2024_v1_2_1-d1.xml \
+ --ugt v1.26.0 \
+ --build 0x118f \
  -p ~/work_synth/production
 ```
 
 After all syntheses have finished, check results:
 
 ```bash
-python scripts/check_synth_ipbb.py <path of build_xxxx.cfg>
+ugt-checksynth <path of build_xxxx.cfg>
 ```
 
 If timing errors occur (and bit files is not generated), check timing errors in file:
@@ -242,13 +217,13 @@ If timing errors occur (and bit files is not generated), check timing errors in
 Afterwards execute the following command for every module with timing errors to generate bit file:
 
 ```bash
-vivado -mode batch -source <path to scripts/vivado_write_bitstream.tcl> -tclargs <project path> <module id (e.g.: 0)>
+vivado -mode batch -source <path to scripts/vivado_write_bitstream.tcl> -tclargs <project path> <module id>
 ```
 
 After successfully created bit files, execute the following command to create tar file for HW:
 
 ```bash
-python scripts/fwpacker_ipbb.py <path of build_xxxx.cfg>
+ugt-fwpacker <path of build_xxxx.cfg>
 ```
 
 ## Build single module

firmware/cfg/uGT_algo.dep

@@ -79,6 +79,7 @@ src payload/gtl/correlation_cuts_calculation.vhd
 src payload/gtl/correlation_conditions.vhd
 src payload/gtl/zdc_condition.vhd
 src payload/gtl/cicada_condition.vhd
+src payload/gtl/calo_comb_multi_condition.vhd
 #
 ### modules of BRAMs used for mass over DeltaR
 ## XCI files of blk_mem_gen for rom_lut_calo_inv_dr_sq and rom_lut_muon_inv_dr_sq moved to 'add_l1menu_blkmem_files.tcl'

firmware/hdl/packages/gt_mp7_core_pkg.vhd

@@ -4,12 +4,12 @@
 -- actual versions:
 -- use "FRAME_VERSION" as mp7_ugt release fw version (used for tag name).
 
--- mp7_ugt (=FRAME_VERSION): v1.26.0
+-- mp7_ugt (=FRAME_VERSION): v1.27.0
 
 -- use "GT_VERSION" as mp7_ugt release fw version (used for tag name).
--- gt: v1.26.0
+-- gt: v1.27.0
 -- frame: v1.4.2 (see frame.vhd)
--- gtl: v1.20.0 (see gtl_module_tpl.vhd)
+-- gtl: v1.21.0 (see gtl_module_tpl.vhd)
 -- fdl: v1.4.1 (see fdl_module.vhd)
 
 -- HB 2023-04-08: v1.22.2 - Changed in scripts/mp7_patch.py (for area_constraints.tcl).
@@ -36,6 +36,7 @@
 --
 -- gtl history:
 
+-- HB 2024-05-23: v1.21.0: Implemented HTMHF and calo comb multi condition.
 -- HB 2023-12-18: v1.20.0: Implemented topological and cicada trigger.
 -- HB 2023-09-29: v1.19.4: Used "no_mgt" at quads 8..16 (top_decl.vhd).
 -- HB 2023-09-28: v1.19.3: Used "no_chk" and "no_buf" at quads 8..16 (top_decl.vhd).
@@ -99,7 +100,7 @@ package gt_mp7_core_pkg is
 -- ==================================================================================================
 -- GT firmware version
     constant GT_MAJOR_VERSION      : integer range 0 to 255 := 1;
-    constant GT_MINOR_VERSION      : integer range 0 to 255 := 26;
+    constant GT_MINOR_VERSION      : integer range 0 to 255 := 27;
     constant GT_REV_VERSION        : integer range 0 to 255 := 0;
 	constant GT_VERSION : std_logic_vector(31 downto 0) := X"00" &
            std_logic_vector(to_unsigned(GT_MAJOR_VERSION, 8)) &
@@ -111,7 +112,7 @@ package gt_mp7_core_pkg is
     constant FRAME_REV_VERSION        : integer range 0 to 255 := 2;
 -- GTL firmware (fix part) version
     constant GTL_FW_MAJOR_VERSION      : integer range 0 to 255 := 1;
-    constant GTL_FW_MINOR_VERSION      : integer range 0 to 255 := 20;
+    constant GTL_FW_MINOR_VERSION      : integer range 0 to 255 := 21;
     constant GTL_FW_REV_VERSION        : integer range 0 to 255 := 0;
 -- FDL firmware version
     constant FDL_FW_MAJOR_VERSION      : integer range 0 to 255 := 1;

firmware/hdl/packages/gtl_pkg.vhd

@@ -2,6 +2,7 @@
 -- Package for constant and type definitions of GTL firmware in Global Trigger Upgrade system.
 
 -- Version history:
+-- HB 2024-05-10: added COMMON_COND_STAGES for condition with no intermediate pipeline.
 -- HB 2023-10-10: CICADA definition changed: no bjets.
 -- HB 2023-10-03: inserted calo anomaly algorithm (CICADA) definitions.
 -- HB 2023-09-13: NR_INPUT_LANES not used anymore. Added type lword_array (for output_mux.vhd and mux.vhd)
@@ -82,17 +83,18 @@ type lword_array is array (0 to LINK_FRAMES-1) of lword;
 
 -- Fixed pipeline structure
 constant BX_PIPELINE_STAGES: natural := 5; -- +/- 2bx pipeline
-constant ESUMS_COND_STAGES: natural := 2; -- pipeline stages for "External conditions" to get same pipeline to algos as conditions
-constant MB_COND_STAGES: natural := 2; -- pipeline stages for "Minimum Bias conditions" to get same pipeline to algos as conditions
-constant TC_COND_STAGES: natural := 2; -- pipeline stages for "Towercount condition" to get same pipeline to algos as conditions
-constant EXT_COND_STAGES: natural := 2; -- pipeline stages for "External conditions" to get same pipeline to algos as conditions
-constant CENTRALITY_STAGES: natural := 2; -- pipeline stages for "Centrality" to get same pipeline to algos as conditions
-constant MUS_STAGES: natural := 2; -- pipeline stages for "Hadronic shower triggers (muon)" to get same pipeline to algos as conditions
+constant COMMON_COND_STAGES: natural := 2; -- pipeline stages for condition with no intermediate pipeline
+constant ESUMS_COND_STAGES: natural := COMMON_COND_STAGES; -- pipeline stages for "External conditions" to get same pipeline to algos as conditions
+constant MB_COND_STAGES: natural := COMMON_COND_STAGES; -- pipeline stages for "Minimum Bias conditions" to get same pipeline to algos as conditions
+constant TC_COND_STAGES: natural := COMMON_COND_STAGES; -- pipeline stages for "Towercount condition" to get same pipeline to algos as conditions
+constant EXT_COND_STAGES: natural := COMMON_COND_STAGES; -- pipeline stages for "External conditions" to get same pipeline to algos as conditions
+constant CENTRALITY_STAGES: natural := COMMON_COND_STAGES; -- pipeline stages for "Centrality" to get same pipeline to algos as conditions
+constant MUS_STAGES: natural := COMMON_COND_STAGES; -- pipeline stages for "Hadronic shower triggers (muon)" to get same pipeline to algos as conditions
+constant ZDC_STAGES: natural := COMMON_COND_STAGES; -- pipeline stages for "ZDC condition" to get same pipeline to algos as conditions
+constant CICADA_COND_STAGES: natural := COMMON_COND_STAGES; -- pipeline stages for "CICADA conditions" to get same pipeline to algos as conditions
 constant ADT_SIM_DEL: natural := 2; -- delay of ADT for simulation 
-constant ZDC_STAGES: natural := 2; -- pipeline stages for "ZDC condition" to get same pipeline to algos as conditions
 constant INTERMEDIATE_PIPELINE: boolean := true; -- intermediate pipeline
 constant CONDITIONS_PIPELINE: boolean := true; -- pipeline at output of conditions
-constant CICADA_COND_STAGES: natural := 2; -- pipeline stages for "CICADA conditions" to get same pipeline to algos as conditions
 
 -- Selector for options
 constant SPYMEM: boolean := true; -- selector for input spymem

firmware/hdl/payload/gtl/calo_comb_multi_condition.vhd

@@ -0,0 +1,55 @@
+
+-- Description:
+-- Trigger on a given object number and threshold (equal for all objects)
+-- "... like 6 jets with pT > 15 GeV or 8-10 jets with no pT requirement" - mail from Efe Ygitbasi (2024-05-08)
+
+-- Version history:
+-- HB 2024-05-08: first design.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+use work.gtl_pkg.all;
+
+entity calo_comb_multi_condition is
+    generic	(
+        nr_obj : natural := 6;
+        pt_width : natural := JET_ET_BITS;
+        pt_threshold: std_logic_vector;
+        pt_ge_mode: boolean := true
+    );
+    port(
+        clk : in std_logic;
+        data_i: in calo_objects_array(0 to MAX_CALO_OBJECTS-1);
+        condition_o : out std_logic
+    );
+end calo_comb_multi_condition;
+
+architecture rtl of calo_comb_multi_condition is
+
+    signal pt : std_logic_vector(pt_width-1 downto 0) := (others => '0');
+    signal comp : std_logic;
+    signal comp_v, comp_v_o : std_logic_vector(0 downto 0);
+
+begin
+
+    pt <= data_i(nr_obj-1)(pt_width-1 downto 0);
+
+    comp <= '1' when pt >= pt_threshold and pt_ge_mode else
+            '1' when pt = pt_threshold and not pt_ge_mode else '0';
+
+    comp_v(0) <= comp;
+
+    out_pipe_i: entity work.delay_pipeline
+        generic map(
+            DATA_WIDTH => 1,
+            STAGES => COMMON_COND_STAGES
+        )
+        port map(
+            clk, comp_v, comp_v_o
+        );
+
+    condition_o <= comp_v_o(0);
+
+end architecture rtl;

firmware/hdl/payload/gtl_module_tpl.vhd

@@ -2,6 +2,7 @@
 -- Global Trigger Logic module.
 
 -- Version history:
+-- HB 2024-05-23: v1.21.0: Implemented HTMHF and calo comb multi condition.
 -- HB 2023-12-18: v1.20.0: Implemented topological and cicada trigger.
 -- HB 2023-09-29: v1.19.4: Used "no_mgt" at quads 8..16 (top_decl.vhd).
 -- HB 2023-09-28: v1.19.3: Used "no_chk" and "no_buf" at quads 8..16.