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GEM-CSC Trigger for Run-3 #34582
GEM-CSC Trigger for Run-3 #34582
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…rue muon to LCT matching is based on ALCT-LCT or CLCT-LCT match
Plots showing efficiency of simulated muon to match to an LCT in ME1/1 or ME2/1. The matching is done like so: sim muon -> CSC simhits -> CSC digis -> CSC ALCT/CLCT -> CSC LCT. At least 3 simhits are required in a chamber (but usually there are 6). Final step of the matching requires either an ALCT-to-LCT or CLCT-to-LCT match. We typically don't require both because (1) ALCT-2GEM and CLCT-2GEM LCTs are missing half the CSC information (2) in cases with 2 ALCT and 2 CLCTs it's possible that the trigger decided a different pairing than what is in the MC truth information. LCT efficiency (CSC trigger) for 10 GeV prompt muons in ME1/1 without pileup LCT efficiency (GEM-CSC trigger) for 10 GeV prompt muons in ME1/1 without pileup LCT efficiency (CSC trigger) for 10 GeV prompt muons in ME2/1 without pileup LCT efficiency (GEM-CSC trigger) for 10 GeV prompt muons in ME2/1 without pileup |
Seems like the only PU200 relval with a decent GE2/1 geometry is |
+code-checks Logs: https://cmssdt.cern.ch/SDT/code-checks/cms-sw-PR-34582/24133 |
A new Pull Request was created by @dildick (Sven Dildick) for master. It involves the following packages:
@andrius-k, @kmaeshima, @ErnestaP, @ahmad3213, @cmsbuild, @rekovic, @jfernan2, @cecilecaillol, @rvenditti can you please review it and eventually sign? Thanks. cms-bot commands are listed here |
@cecilecaillol After this, I expect another PR to enable the GEM-CSC matching based on the CCLUT slope, and some fine-tuning of the matching parameters. But probably nothing as big as the past few PRs... All the machinery is in place. We have not yet developed the GEM-CSC bending angle assignment in the CorrelatedLCTDigi. Likely we will start working on this next as well. |
please test |
-1 Failed Tests: ClangBuild Clang BuildI found compilation warning while trying to compile with clang. Command used:
See details on the summary page. |
-1 Failed Tests: RelVals RelVals
|
The relval failure is not related to this PR. |
+l1 |
@dildick despite the relval failure is not related to the changes in this PR, I'd like to see a complete check of the PR to get the DQM comparison since none of the trials performed so far concluded, so I am retriggering the tests again |
please test |
+1 Summary: https://cmssdt.cern.ch/SDT/jenkins-artifacts/pull-request-integration/PR-f15eca/17134/summary.html Comparison SummarySummary:
|
+1 |
This pull request is fully signed and it will be integrated in one of the next master IBs (tests are also fine). This pull request will now be reviewed by the release team before it's merged. @silviodonato, @dpiparo, @qliphy, @perrotta (and backports should be raised in the release meeting by the corresponding L2) |
@jfernan2 Thanks for the quick turn-around. There are a few minor changes in the L1T CSC DQM, but that's expected since we enhanced ME1/1 and/or ME2/1 LCTs depending on the era. |
And there are no differences in Run-1 or Run-2 scenarios. I was not expecting any. |
In all the performance with the tests look good. That will be it for CSC and GEM-CSC trigger for a while. I have all features for CMSSW_12_0_0_pre5 in. There will be a few updates in late Summer or Fall for GEM-CSC trigger, but nothing major. @qliphy If you want to sign this PR. Thanks. |
+1 |
PR description:
This PR puts in place the missing pieces for the GEM-CSC trigger for Run-3
CSCUpgradeMotherboard
, and absorbedCSCGEMMotherboardME11
andCSCGEMMotherboardME21
intoCSCGEMMotherboard
. There are now just two motherboards remaining (CSCMotherboard
andCSCGEMMotherboard
) down from 6. The old GEM processor (GEMCoPadProcessor
) and an obsolete lookup table classCSCUpgradeMotherboardLUT
were deleted.CSCTriggerPrimitivesBuilder
a lot simpler.CSCLUTReader
and LUTs in https://github.com/cms-data/L1Trigger-CSCTriggerPrimitives/tree/master/GEMCSC/CoordinateConversion.CSCMuonPortCard
. After all, the QC class is designed to operate on a single (O)TMB, rather than on an entire endcap trigger sector.GEMInternalCluster
class members are properly initialized in the constructor.Follow-up of #34513, #33974 and #33570.
Documentation is being compiled in a detector note (should be ready by end of the Summer).
PR validation:
Tested the code so far on
/RelValSingleMuPt10/CMSSW_11_3_0-113X_mcRun4_realistic_v7_2026D76noPU-v1/GEN-SIM-DIGI-RAW
. A few efficiency plots are added below.Efficiency is ~98% in ME1/1 across the eta range. Efficiency is ~98% in ME2/1 across the eta range, except for near |eta|~1.8 and 2.05 where the high voltage drops. This drop can be mitigated if the number of layers on an ALCT is reduced to 3. However, because the backgrounds in Phase-2 not well understood I am keeping the number of layers to at least 4.
I ran interactively on a few thousand events. I did not see any LogWarnings from the
LCTQualityControl
class about potentially invalid ALCTs, CLCTs or LCTs.I'll also check the performance on PU200, but that should be largely unaffected.
if this PR is a backport please specify the original PR and why you need to backport that PR:
N/A
Before submitting your pull requests, make sure you followed this checklist:
FYI @tahuang1991 @rathjd