Fixup: Re-enable the VHDL library tests

cocotb · Jun 28, 2023 · c9d729c · c9d729c
1 parent 2f02888
commit c9d729c
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/tests/test_cases/test_vhdl_libraries/Makefile b/tests/test_cases/test_vhdl_libraries/Makefile
@@ -12,15 +12,15 @@ ifneq ($(filter $(SIM),xcelium),)
     COMPILE_ARGS += -v93
 endif
 
-ifneq ($(filter questa modelsim xcelium ius,$(shell echo $(SIM) | tr A-Z a-z)),)
+ifneq ($(filter questa-compat questa-qisqrun modelsim xcelium ius,$(shell echo $(SIM) | tr A-Z a-z)),)
     VHDL_LIB_ORDER := blib
 endif
 
 ifneq ($(shell echo $(TOPLEVEL_LANG) | tr A-Z a-z),vhdl)
 all:
 	@echo "Skipping test since only VHDL is supported"
 clean::
-else ifeq ($(filter ghdl questa modelsim xcelium ius,$(shell echo $(SIM) | tr A-Z a-z)),)
+else ifeq ($(filter ghdl questa-compat questa-qisqrun modelsim xcelium ius,$(shell echo $(SIM) | tr A-Z a-z)),)
 all:
 	@echo "Skipping test since only GHDL, Questa/ModelSim, Xcelium and Incisive are supported"
 clean::

diff --git a/tests/test_cases/test_vhdl_libraries_multiple/Makefile b/tests/test_cases/test_vhdl_libraries_multiple/Makefile
@@ -17,15 +17,15 @@ ifneq ($(filter $(SIM),xcelium),)
     COMPILE_ARGS += -v93
 endif
 
-ifneq ($(filter questa modelsim xcelium,$(shell echo $(SIM) | tr A-Z a-z)),)
+ifneq ($(filter questa questa-compat questa-qisqrun modelsim xcelium,$(shell echo $(SIM) | tr A-Z a-z)),)
     VHDL_LIB_ORDER := elib dlib clib blib
 endif
 
 ifneq ($(shell echo $(TOPLEVEL_LANG) | tr A-Z a-z),vhdl)
 all:
 	@echo "Skipping test since only VHDL is supported"
 clean::
-else ifeq ($(filter ghdl questa modelsim xcelium,$(shell echo $(SIM) | tr A-Z a-z)),)
+else ifeq ($(filter ghdl questa-compat questa-qisqrun modelsim xcelium,$(shell echo $(SIM) | tr A-Z a-z)),)
 all:
 	@echo "Skipping test since only GHDL, Questa/ModelSim and Xcelium are supported"
 clean::