Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Fix extension for files that are SystemVerilog. #1071

Merged
merged 1 commit into from Aug 17, 2019
Merged

Fix extension for files that are SystemVerilog. #1071

merged 1 commit into from Aug 17, 2019

Conversation

cmarqu
Copy link
Contributor

@cmarqu cmarqu commented Aug 16, 2019

These files use typedef and are thus SystemVerilog really, so fix their extension. This makes them automatically compile in Cadence simulators without further switches.

eric-wieser
eric-wieser approved these changes Aug 16, 2019
View reviewed changes
Copy link
Member

@eric-wieser eric-wieser left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Seems reasonable

@themperek
Copy link
Contributor

Thank you @cmarqu and @eric-wieser.

@themperek themperek merged commit 7de14fb into cocotb:master Aug 17, 2019
@cmarqu cmarqu deleted the fix-extension-for-sv-files branch August 17, 2019 10:59
@imphil imphil added this to the 1.3 milestone Aug 26, 2019
@cmarqu cmarqu restored the fix-extension-for-sv-files branch February 27, 2022 17:37
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@eric-wieser eric-wieser eric-wieser approved these changes

Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
1.3
Development

Successfully merging this pull request may close these issues.

None yet
4 participants
@cmarqu @themperek @eric-wieser @imphil