A bitslice implementation of a Physical Unclonable Function, this Arbiter PUF has eight stages of two
2:1 multiplexers for the challenge circuit and two cross-coupled NAND gates for the response/arbiter circuit.
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A bitslice implementation of a Physical Unclonable Function, this Arbiter PUF has eight stages of two 2:1 multiplexers for the challenge circuit and two cross-coupled NAND gates for the response/arbiter circuit.
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cole-maxwell/arbiter_puf
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A bitslice implementation of a Physical Unclonable Function, this Arbiter PUF has eight stages of two 2:1 multiplexers for the challenge circuit and two cross-coupled NAND gates for the response/arbiter circuit.
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