Pinned

1. n_tap_fir_filter_arm n_tap_fir_filter_arm Public

   Modular design of an N-tap FIR filter on the DE1-SoC’s FPGA; synthesis in Quartus Prime, code in Verilog, VHDL & C.

   SystemVerilog 3

2. Gamma_Filter_DE1_SoC_FPGA Gamma_Filter_DE1_SoC_FPGA Public

   FPGA implementation (on DE1-SoC) of a gamma power function, which improves the clarity of the video output by transforming the intensity values of each pixel value in every frame of video input.

   Verilog 7 3

3. network_on_chip network_on_chip Public

   Simulation, synthesis, and physical design for an NoC. Each tile of the chip multiprocessor (CMP) NoC has a router and associated processing core.

   Verilog 4 1

4. arbiter_puf arbiter_puf Public

   A bitslice implementation of a Physical Unclonable Function, this Arbiter PUF has eight stages of two 2:1 multiplexers for the challenge circuit and two cross-coupled NAND gates for the response/ar…

   Python 3

5. bitslice_accumulator bitslice_accumulator Public

   Design, layout, and analysis of an accumulator bitslice consisting of a full adder and a resettable flip-flop.

   Python 1

6. combinational_cmos_multiplexer combinational_cmos_multiplexer Public

   Design, layout, parasitic extraction & analysis of a 2:1 multiplexer. Use HSPICE, Cscope, and Virtuoso to to run experiments and observe how circuit metrics vary with supply voltage, load capacitan…

   Python 2