soc/intel/tigerlake: Remove Jasper Lake SoC references

This implementation removes all JSL references from the TGL SoC code.
Additionally, mainboard code changes are done to support build.

BUG=b:150217037
TEST=build tglrvp and volteer

Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/volteer/romstage.c

@@ -8,7 +8,7 @@
 #include <baseboard/variants.h>
 #include <gpio.h>
 #include <soc/gpio.h>
-#include <soc/meminit_tgl.h>
+#include <soc/meminit.h>
 #include <soc/romstage.h>
 #include <variant/gpio.h>
 

src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h

@@ -9,7 +9,7 @@
 #define __BASEBOARD_VARIANTS_H__
 
 #include <soc/gpio.h>
-#include <soc/meminit_tgl.h>
+#include <soc/meminit.h>
 #include <stddef.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 

src/mainboard/intel/tglrvp/romstage_fsp_params.c

@@ -17,7 +17,7 @@
 #include <soc/romstage.h>
 #include <spd_bin.h>
 #include <string.h>
-#include <soc/meminit_tgl.h>
+#include <soc/meminit.h>
 #include <baseboard/variants.h>
 #include <cbfs.h>
 #include "board_id.h"

src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h

@@ -16,7 +16,7 @@
 #define __BASEBOARD_VARIANTS_H__
 
 #include <soc/gpio.h>
-#include <soc/meminit_tgl.h>
+#include <soc/meminit.h>
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 

src/soc/intel/tigerlake/Kconfig

@@ -72,13 +72,12 @@ config DCACHE_RAM_SIZE
 
 config DCACHE_BSP_STACK_SIZE
 	hex
-	default 0x40400 if SOC_INTEL_TIGERLAKE
-	default 0x30400 if SOC_INTEL_JASPERLAKE
+	default 0x40400
 	help
 	  The amount of anticipated stack usage in CAR by bootblock and
 	  other stages. In the case of FSP_USES_CB_STACK default value will be
-	  sum of FSP-M stack requirement (256KiB for TGL, 192KiB for JSL) and CB romstage
-	  stack requirement (~1KiB).
+	  sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement
+	  (~1KiB).
 
 config FSP_TEMP_RAM_SIZE
 	hex
@@ -90,8 +89,7 @@ config FSP_TEMP_RAM_SIZE
 
 config IFD_CHIPSET
 	string
-	default "jsl" if SOC_INTEL_JASPERLAKE
-	default "tgl" if SOC_INTEL_TIGERLAKE
+	default "tgl"
 
 config IED_REGION_SIZE
 	hex
@@ -103,13 +101,11 @@ config HEAP_SIZE
 
 config MAX_ROOT_PORTS
 	int
-	default 8 if SOC_INTEL_JASPERLAKE
-	default 12 if SOC_INTEL_TIGERLAKE
+	default 12
 
 config MAX_PCIE_CLOCKS
 	int
-	default 7 if SOC_INTEL_TIGERLAKE
-	default 6 if SOC_INTEL_JASPERLAKE
+	default 7
 
 config SMM_TSEG_SIZE
 	hex
@@ -143,8 +139,7 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 
 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 	int
-	default 3 if SOC_INTEL_JASPERLAKE
-	default 4 if SOC_INTEL_TIGERLAKE
+	default 4
 
 config SOC_INTEL_I2C_DEV_MAX
 	int
@@ -162,16 +157,13 @@ config CONSOLE_UART_BASE_ADDRESS
 # Clock divider parameters for 115200 baud rate
 # Baudrate = (UART source clcok * M) /(N *16)
 # TGL UART source clock: 120MHz
-# JSL UART source clock: 100MHz
 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 	hex
-	default 0x30 if SOC_INTEL_JASPERLAKE
-	default 0x25a if SOC_INTEL_TIGERLAKE
+	default 0x25a
 
 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 	hex
-	default 0xc35 if SOC_INTEL_JASPERLAKE
-	default 0x7fff if SOC_INTEL_TIGERLAKE
+	default 0x7fff
 
 config CHROMEOS
 	select CHROMEOS_RAMOOPS_DYNAMIC
@@ -193,14 +185,12 @@ config CBFS_SIZE
 
 config FSP_HEADER_PATH
 	string "Location of FSP headers"
-	default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" if SOC_INTEL_JASPERLAKE
-	default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" if SOC_INTEL_TIGERLAKE
+	default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/"
 
 config FSP_FD_PATH
 	string
 	depends on FSP_USE_REPO
-	default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE
-	default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE
+	default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd"
 
 config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT
 	int "Debug Consent for TGL"

src/soc/intel/tigerlake/Makefile.inc

@@ -20,15 +20,12 @@ bootblock-y += bootblock/cpu.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += espi.c
-bootblock-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c
-bootblock-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c
+bootblock-y += gpio.c
 bootblock-y += p2sb.c
 
 romstage-y += espi.c
-romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += meminit_tgl.c
-romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += meminit_jsl.c
-romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c
-romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c
+romstage-y += meminit.c
+romstage-y += gpio.c
 romstage-y += reset.c
 
 ramstage-y += acpi.c
@@ -37,10 +34,8 @@ ramstage-y += cpu.c
 ramstage-y += elog.c
 ramstage-y += espi.c
 ramstage-y += finalize.c
-ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c
-ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c
-ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c
-ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c
+ramstage-y += fsp_params.c
+ramstage-y += gpio.c
 ramstage-y += graphics.c
 ramstage-y += lockdown.c
 ramstage-y += p2sb.c
@@ -50,15 +45,14 @@ ramstage-y += smmrelocate.c
 ramstage-y += systemagent.c
 ramstage-y += sd.c
 
-smm-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c
-smm-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c
+smm-y += gpio.c
 smm-y += p2sb.c
 smm-y += pmc.c
 smm-y += pmutil.c
 smm-y += smihandler.c
 smm-y += uart.c
 
-verstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c
+verstage-y += gpio.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/tigerlake
 CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include

src/soc/intel/tigerlake/acpi/pci_irqs.asl

@@ -13,8 +13,155 @@
  * GNU General Public License for more details.
  */
 
-#if CONFIG(SOC_INTEL_TIGERLAKE)
-	#include "pci_irqs_tgl.asl"
-#else
-	#include "pci_irqs_jsl.asl"
-#endif
+#include <soc/irq.h>
+
+Name (PICP, Package () {
+	/* D31:HSA, SMBUS, TraceHUB */
+	Package(){0x001FFFFF, 3, 0, HDA_IRQ },
+	Package(){0x001FFFFF, 4, 0, SMBUS_IRQ },
+	Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ },
+	/* D30: UART0, UART1, SPI0, SPI1 */
+	Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
+	Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
+	Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
+	Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
+	/* D29: RP9 ~ RP12 */
+	Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
+	Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
+	Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
+	Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
+	/* D28: RP1 ~ RP8 */
+	Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
+	Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
+	Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
+	Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
+	Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ },
+	Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ },
+	Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ },
+	Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ },
+	/* D25: I2C4, I2C5, UART2 */
+	Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
+	Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
+	Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
+	/* D23: SATA */
+	Package(){0x0017FFFF, 0, 0, SATA_IRQ },
+	/* D22: CSME */
+	Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
+	Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
+	Package(){0x0016FFFF, 4, 0, HECI_3_IRQ },
+	Package(){0x0016FFFF, 5, 0, HECI_4_IRQ },
+	/* D21: I2C0 ~ I2C3 */
+	Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
+	Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
+	Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
+	Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
+	/* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
+	Package(){0x0014FFFF, 0, 0, xHCI_IRQ },
+	Package(){0x0014FFFF, 1, 0, xDCI_IRQ },
+	Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ },
+	/* D19: SPI3 */
+	Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ },
+	/* D18: ISH, SPI2 */
+	Package(){0x0012FFFF, 0, 0, ISH_IRQ },
+	Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ },
+	/* D16: CNVI_BT, TCH0, TCH1 */
+	Package(){0x0010FFFF, 2, 0, CNVI_BT_IRQ },
+	Package(){0x0010FFFF, 6, 0, THC0_IRQ },
+	Package(){0x0010FFFF, 7, 0, THC1_IRQ },
+	/* D13: xHCI, xDCI */
+	Package(){0x000DFFFF, 0, 0, xHCI_IRQ },
+	Package(){0x000DFFFF, 1, 0, xDCI_IRQ },
+	/* D8: GNA */
+	Package(){0x0008FFFF, 0, 0, GNA_IRQ },
+	/* D7: TBT PCIe */
+	Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ },
+	Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ },
+	Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ },
+	Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ },
+	/* D6: PEG60 */
+	Package(){0x0006FFFF, 0, 0, PEG_IRQ },
+	/* D5: IPU Device */
+	Package(){0x0005FFFF, 0, 0, IPU_IRQ },
+	/* D4:  Thermal Device */
+	Package(){0x0004FFFF, 0, 0, THERMAL_IRQ },
+	/* D2: IGFX */
+	Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
+})
+
+Name (PICN, Package () {
+	/* D31:HSA, SMBUS, TraceHUB*/
+	Package () { 0x001FFFFF, 3, 0, 11 },
+	Package () { 0x001FFFFF, 4, 0, 11 },
+	Package () { 0x001FFFFF, 7, 0, 11 },
+	/* D30: UART0, UART1, SPI0, SPI1 */
+	Package () { 0x001EFFFF, 0, 0, 11 },
+	Package () { 0x001EFFFF, 1, 0, 10 },
+	Package () { 0x001EFFFF, 2, 0, 11 },
+	Package () { 0x001EFFFF, 3, 0, 11 },
+	/* D29: RP9 ~ RP12 */
+	Package () { 0x001DFFFF, 0, 0, 11 },
+	Package () { 0x001DFFFF, 1, 0, 10 },
+	Package () { 0x001DFFFF, 2, 0, 11 },
+	Package () { 0x001DFFFF, 3, 0, 11 },
+	/* D28: RP1 ~ RP8 */
+	Package () { 0x001CFFFF, 0, 0, 11 },
+	Package () { 0x001CFFFF, 1, 0, 10 },
+	Package () { 0x001CFFFF, 2, 0, 11 },
+	Package () { 0x001CFFFF, 3, 0, 11 },
+	Package () { 0x001CFFFF, 4, 0, 11 },
+	Package () { 0x001CFFFF, 5, 0, 10 },
+	Package () { 0x001CFFFF, 6, 0, 11 },
+	Package () { 0x001CFFFF, 7, 0, 11 },
+	/* D25: I2C4, I2C5, UART2 */
+	Package(){0x0019FFFF, 0, 0, 11 },
+	Package(){0x0019FFFF, 1, 0, 10 },
+	Package(){0x0019FFFF, 2, 0, 11 },
+	/* D23: SATA */
+	Package () { 0x0017FFFF, 0, 0, 11 },
+	/* D22: CSME */
+	Package(){0x0016FFFF, 0, 0, 11 },
+	Package(){0x0016FFFF, 1, 0, 10 },
+	Package(){0x0016FFFF, 4, 0, 11 },
+	Package(){0x0016FFFF, 5, 0, 11 },
+	/* D21: I2C0 ~ I2C3 */
+	Package(){0x0015FFFF, 0, 0, 11 },
+	Package(){0x0015FFFF, 1, 0, 10 },
+	Package(){0x0015FFFF, 2, 0, 11 },
+	Package(){0x0015FFFF, 3, 0, 11 },
+	/* D19: SPI3 */
+	Package(){0x0013FFFF, 0, 0, 11 },
+	/* D18: ISH, SPI2 */
+	Package(){0x0012FFFF, 0, 0, 11 },
+	Package(){0x0012FFFF, 6, 0, 11 },,
+	/* D16: CNVI_BT, TCH0, TCH1 */
+	Package(){0x0010FFFF, 2, 0, 11 },
+	Package(){0x0010FFFF, 6, 0, 11 },
+	Package(){0x0010FFFF, 7, 0, 10 },
+	/* D13: xHCI, xDCI */
+	Package(){0x000DFFFF, 0, 0, 11 },
+	Package(){0x000DFFFF, 1, 0, 10 },
+	/* D8: GNA */
+	Package(){0x0008FFFF, 0, 0, 11 },
+	/* D7: TBT PCIe */
+	Package(){0x0007FFFF, 0, 0, 11 },
+	Package(){0x0007FFFF, 1, 0, 10 },
+	Package(){0x0007FFFF, 2, 0, 11 },
+	Package(){0x0007FFFF, 3, 0, 11 },
+	/* D6: PEG60 */
+	Package(){0x0006FFFF, 0, 0, 11 },
+	/* D5: IPU Device */
+	Package(){0x0005FFFF, 0, 0, 11 },
+	/* D4:  Thermal Device */
+	Package(){0x0004FFFF, 0, 0, 11 },
+	/* D2: IGFX */
+	Package(){0x0002FFFF, 0, 0, 11 },
+})
+
+Method (_PRT)
+{
+	If (PICM) {
+		Return (^PICP)
+	} Else {
+		Return (^PICN)
+	}
+}