Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Prototypical implementation of an app custom interface pass-through approach #173

Conversation

Basseuph
Copy link
Contributor

@Basseuph Basseuph commented Nov 6, 2023

Overview

As discussed in past dev meetings, MLE, more specifically Oskar, provides a prototype for the proposed way to pass custom interfaces through the mqnic hierarchies into the APP.
If this prototypical implementation is the way to go, we are happy to apply this approach to the existing template and dma_bench apps, as well as to all the modules in the hierarchy and the implementations (i.e. adapting the makefiles, etc.), and create a separate pull request or rewrite the branch this PR is based on.

The idea is to use verilog defines provided by a customizable verilog header file to add

  1. a set of parameters that could be used by the custom interfaces
  2. a set of ports to be added to the modules
  3. a set of port connections to the instances within the modules

The existence of the header file is mandatory, but it would be provided alongside the future template app then.

Implementation

To prove that the approach is actually feasible, we created an additional app and ZCU102 based design implementing this app.
We also copied the relevant core files to be enriched with the macros. To test if everything works as intended and at least the Vivado flow is not affected by the changes, we “redirect” the AXI-L slave interface of mqnic_app (s_axil_app_ctrl_*)back up through the hierarchy, where it is then used to control the board LEDs on the top level.

Commit b1bb6dd duplicates the template app infrastructure for the prototype app.

Commit 3737311 adds a copy of infrastructure modules.
The next commit assembles the project together and adapts the APP_ID, see commit f6b8b9f.

The next step adds the verilog macros to the various places, see commit 7132f66.
The last commit establishes the demo functionality by adding an AXI-L register to fpga_core and connecting the custom interface within the mqnic_app_block. See commit fdd62c6.

Next Steps

Does this implementation reflect the idea of passing custom interfaces through the hierarchies to the app? Should we modify the branch this PR is based on to then provide a pullable version?

@Basseuph
Copy link
Contributor Author

After the discussions and tests based on the proposed prototypical implementation, we now have the new PR #179 in place, so we can close this one.

@Basseuph Basseuph closed this Dec 20, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

None yet

2 participants