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x393_testbench01.sav
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x393_testbench01.sav
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[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Sat Aug 1 01:57:02 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150731124427127.lxt"
[dumpfile_mtime] "Fri Jul 31 19:02:35 2015"
[dumpfile_size] 1073757835
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 38799000
[size] 1823 1180
[pos] 1919 0
*-18.877661 39967388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.ddr3_i.
[treeopen] x393_testbench01.x393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
[treeopen] x393_testbench01.x393_i.sync_resets_i.
[treeopen] x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.
[treeopen] x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].
[treeopen] x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.
[treeopen] x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.
[sst_width] 363
[signals_width] 446
[sst_expanded] 1
[sst_vpaned_height] 550
@820
x393_testbench01.TEST_TITLE[639:0]
@800200
-DDR3
@28
x393_testbench01.SDRST[0]
x393_testbench01.SDCLK[0]
x393_testbench01.SDBA[2:0]
@22
x393_testbench01.SDA[14:0]
@28
x393_testbench01.SDRAS[0]
x393_testbench01.SDCAS[0]
x393_testbench01.SDWE[0]
x393_testbench01.SDODT[0]
x393_testbench01.DQSL[0]
x393_testbench01.DQSU[0]
@22
x393_testbench01.SDD[15:0]
@1000200
-DDR3
@c00200
-top
@28
x393_testbench01.CLK[0]
x393_testbench01.RST[0]
x393_testbench01.HCLK[0]
x393_testbench01.memclk[0]
x393_testbench01.ffclk0p[0]
@1401200
-top
@800200
-PS
@22
x393_testbench01.PS_REG_ADDR[31:0]
x393_testbench01.PS_REG_DIN[31:0]
@28
x393_testbench01.PS_REG_WR[0]
x393_testbench01.PS_REG_RD[0]
@22
x393_testbench01.PS_REG_DOUT[31:0]
x393_testbench01.PS_RDATA[31:0]
@1000200
-PS
@c00200
-simul_afi_wr
@22
x393_testbench01.simul_axi_hp_wr_i.write_left[3:0]
x393_testbench01.simul_axi_hp_wr_i.awlen_out[3:0]
@28
x393_testbench01.simul_axi_hp_wr_i.wlast_out[0]
x393_testbench01.simul_axi_hp_wr_i.fifo_wd_rd[0]
x393_testbench01.simul_axi_hp_wr_i.fifo_wd_rd_dly[0]
x393_testbench01.simul_axi_hp_wr_i.last_confirmed_write[0]
@200
-
@28
x393_testbench01.simul_axi_hp_wr_i.WrCmdReleaseMode[1:0]
@22
x393_testbench01.simul_axi_hp_wr_i.WrDataThreshold[3:0]
@28
x393_testbench01.simul_axi_hp_wr_i.aclk[0]
x393_testbench01.simul_axi_hp_wr_i.aresetn[0]
x393_testbench01.simul_axi_hp_wr_i.aw_nempty[0]
@22
x393_testbench01.simul_axi_hp_wr_i.awaddr[31:0]
x393_testbench01.simul_axi_hp_wr_i.awaddr_out[31:0]
@28
x393_testbench01.simul_axi_hp_wr_i.awburst[1:0]
x393_testbench01.simul_axi_hp_wr_i.awburst_out[1:0]
@22
x393_testbench01.simul_axi_hp_wr_i.awcache[3:0]
x393_testbench01.simul_axi_hp_wr_i.awid[5:0]
x393_testbench01.simul_axi_hp_wr_i.awid_out[5:0]
x393_testbench01.simul_axi_hp_wr_i.awlen[3:0]
x393_testbench01.simul_axi_hp_wr_i.awlen_out[3:0]
@28
x393_testbench01.simul_axi_hp_wr_i.awlock[1:0]
x393_testbench01.simul_axi_hp_wr_i.awprot[2:0]
@22
x393_testbench01.simul_axi_hp_wr_i.awqos[3:0]
@28
x393_testbench01.simul_axi_hp_wr_i.awready[0]
x393_testbench01.simul_axi_hp_wr_i.awvalid[0]
@22
x393_testbench01.simul_axi_hp_wr_i.bid[5:0]
x393_testbench01.simul_axi_hp_wr_i.bid_in[5:0]
@28
x393_testbench01.simul_axi_hp_wr_i.bready[0]
x393_testbench01.simul_axi_hp_wr_i.bresp[1:0]
x393_testbench01.simul_axi_hp_wr_i.bresp_in[1:0]
x393_testbench01.simul_axi_hp_wr_i.bresp_value[1:0]
x393_testbench01.simul_axi_hp_wr_i.bvalid[0]
x393_testbench01.simul_axi_hp_wr_i.enough_data[0]
x393_testbench01.simul_axi_hp_wr_i.fifo_addr_we_d[0]
x393_testbench01.simul_axi_hp_wr_i.fifo_data_we_d[0]
x393_testbench01.simul_axi_hp_wr_i.fifo_wd_rd[0]
x393_testbench01.simul_axi_hp_wr_i.fifo_wd_rd_dly[0]
x393_testbench01.simul_axi_hp_wr_i.last_confirmed_write[0]
@22
x393_testbench01.simul_axi_hp_wr_i.next_wr_address[11:3]
x393_testbench01.simul_axi_hp_wr_i.num_full_data[7:0]
x393_testbench01.simul_axi_hp_wr_i.reg_addr[31:0]
x393_testbench01.simul_axi_hp_wr_i.reg_din[31:0]
x393_testbench01.simul_axi_hp_wr_i.reg_dout[31:0]
@28
x393_testbench01.simul_axi_hp_wr_i.reg_rd[0]
x393_testbench01.simul_axi_hp_wr_i.reg_wr[0]
x393_testbench01.simul_axi_hp_wr_i.rst[0]
@22
x393_testbench01.simul_axi_hp_wr_i.sim_bresp_latency[3:0]
x393_testbench01.simul_axi_hp_wr_i.sim_wid[5:0]
x393_testbench01.simul_axi_hp_wr_i.sim_wr_address[31:0]
@28
x393_testbench01.simul_axi_hp_wr_i.sim_wr_cap[2:0]
@22
x393_testbench01.simul_axi_hp_wr_i.sim_wr_data[63:0]
x393_testbench01.simul_axi_hp_wr_i.sim_wr_qos[3:0]
@28
x393_testbench01.simul_axi_hp_wr_i.sim_wr_ready[0]
@22
x393_testbench01.simul_axi_hp_wr_i.sim_wr_stb[7:0]
@28
x393_testbench01.simul_axi_hp_wr_i.sim_wr_valid[0]
x393_testbench01.simul_axi_hp_wr_i.start_write_burst_w[0]
@22
x393_testbench01.simul_axi_hp_wr_i.staticQos[3:0]
@28
x393_testbench01.simul_axi_hp_wr_i.w_nempty[0]
@22
x393_testbench01.simul_axi_hp_wr_i.wacount[5:0]
@28
x393_testbench01.simul_axi_hp_wr_i.was_wresp_re[0]
x393_testbench01.simul_axi_hp_wr_i.wburst[1:0]
@22
x393_testbench01.simul_axi_hp_wr_i.wcount[7:0]
x393_testbench01.simul_axi_hp_wr_i.wdata[63:0]
x393_testbench01.simul_axi_hp_wr_i.wdata_out[63:0]
x393_testbench01.simul_axi_hp_wr_i.wid[5:0]
x393_testbench01.simul_axi_hp_wr_i.wid_out[5:0]
@28
x393_testbench01.simul_axi_hp_wr_i.wlast[0]
@22
x393_testbench01.simul_axi_hp_wr_i.wlen[3:0]
@28
x393_testbench01.simul_axi_hp_wr_i.wr32BitEn[0]
x393_testbench01.simul_axi_hp_wr_i.wrFabricOutCmdEn[0]
x393_testbench01.simul_axi_hp_wr_i.wrFabricQosEn[0]
x393_testbench01.simul_axi_hp_wr_i.wrIssueCap0[2:0]
x393_testbench01.simul_axi_hp_wr_i.wrIssueCap1[2:0]
x393_testbench01.simul_axi_hp_wr_i.wrQosHeadOfCmdQEn[0]
@22
x393_testbench01.simul_axi_hp_wr_i.wr_qos_in[3:0]
x393_testbench01.simul_axi_hp_wr_i.wr_qos_out[3:0]
@28
x393_testbench01.simul_axi_hp_wr_i.wready[0]
@22
x393_testbench01.simul_axi_hp_wr_i.wresp_num_in_fifo[5:0]
@28
x393_testbench01.simul_axi_hp_wr_i.wresp_re[0]
x393_testbench01.simul_axi_hp_wr_i.wrissuecap1en[0]
@22
x393_testbench01.simul_axi_hp_wr_i.write_address[31:0]
@28
x393_testbench01.simul_axi_hp_wr_i.write_in_progress[0]
x393_testbench01.simul_axi_hp_wr_i.write_in_progress_w[0]
@22
x393_testbench01.simul_axi_hp_wr_i.write_left[3:0]
x393_testbench01.simul_axi_hp_wr_i.wstrb[7:0]
x393_testbench01.simul_axi_hp_wr_i.wstrb_out[7:0]
@28
x393_testbench01.simul_axi_hp_wr_i.wvalid[0]
@1401200
-simul_afi_wr
@c00200
-simul_afi_rd
@28
x393_testbench01.simul_axi_hp_rd_i.aclk[0]
x393_testbench01.simul_axi_hp_rd_i.ar_nempty[0]
@22
x393_testbench01.simul_axi_hp_rd_i.araddr[31:0]
x393_testbench01.simul_axi_hp_rd_i.araddr_out[31:0]
@28
x393_testbench01.simul_axi_hp_rd_i.arburst[1:0]
x393_testbench01.simul_axi_hp_rd_i.arburst_out[1:0]
@22
x393_testbench01.simul_axi_hp_rd_i.arcache[3:0]
@28
x393_testbench01.simul_axi_hp_rd_i.aresetn[0]
@22
x393_testbench01.simul_axi_hp_rd_i.arid[5:0]
x393_testbench01.simul_axi_hp_rd_i.arid_out[5:0]
x393_testbench01.simul_axi_hp_rd_i.arlen[3:0]
x393_testbench01.simul_axi_hp_rd_i.arlen_out[3:0]
@28
x393_testbench01.simul_axi_hp_rd_i.arlock[1:0]
x393_testbench01.simul_axi_hp_rd_i.arprot[2:0]
@22
x393_testbench01.simul_axi_hp_rd_i.arqos[3:0]
@28
x393_testbench01.simul_axi_hp_rd_i.arready[0]
x393_testbench01.simul_axi_hp_rd_i.arvalid[0]
@22
x393_testbench01.simul_axi_hp_rd_i.fifo_data_rd[0]
x393_testbench01.simul_axi_hp_rd_i.fifo_with_requested[7:0]
@28
x393_testbench01.simul_axi_hp_rd_i.last_confirmed_read[0]
x393_testbench01.simul_axi_hp_rd_i.last_read[0]
@22
x393_testbench01.simul_axi_hp_rd_i.next_rd_address[11:3]
x393_testbench01.simul_axi_hp_rd_i.next_with_requested[7:0]
@28
x393_testbench01.simul_axi_hp_rd_i.racount[2:0]
x393_testbench01.simul_axi_hp_rd_i.rburst[1:0]
@22
x393_testbench01.simul_axi_hp_rd_i.rcount[7:0]
@28
x393_testbench01.simul_axi_hp_rd_i.rd32BitEn[0]
x393_testbench01.simul_axi_hp_rd_i.rdFabricOutCmdEn[0]
x393_testbench01.simul_axi_hp_rd_i.rdFabricQosEn[0]
x393_testbench01.simul_axi_hp_rd_i.rdIssueCap0[2:0]
x393_testbench01.simul_axi_hp_rd_i.rdIssueCap1[2:0]
x393_testbench01.simul_axi_hp_rd_i.rdQosHeadOfCmdQEn[0]
@22
x393_testbench01.simul_axi_hp_rd_i.rdStaticQos[3:0]
x393_testbench01.simul_axi_hp_rd_i.rd_qos_in[3:0]
x393_testbench01.simul_axi_hp_rd_i.rd_qos_out[3:0]
x393_testbench01.simul_axi_hp_rd_i.rdata[63:0]
@28
x393_testbench01.simul_axi_hp_rd_i.rdissuecap1en[0]
@22
x393_testbench01.simul_axi_hp_rd_i.read_address[31:0]
@28
x393_testbench01.simul_axi_hp_rd_i.read_in_progress[0]
x393_testbench01.simul_axi_hp_rd_i.read_in_progress_w[0]
@22
x393_testbench01.simul_axi_hp_rd_i.read_left[3:0]
x393_testbench01.simul_axi_hp_rd_i.reg_addr[31:0]
x393_testbench01.simul_axi_hp_rd_i.reg_din[31:0]
x393_testbench01.simul_axi_hp_rd_i.reg_dout[31:0]
@28
x393_testbench01.simul_axi_hp_rd_i.reg_rd[0]
x393_testbench01.simul_axi_hp_rd_i.reg_wr[0]
@22
x393_testbench01.simul_axi_hp_rd_i.rid[5:0]
@28
x393_testbench01.simul_axi_hp_rd_i.rlast[0]
@22
x393_testbench01.simul_axi_hp_rd_i.rlen[3:0]
@28
x393_testbench01.simul_axi_hp_rd_i.rready[0]
x393_testbench01.simul_axi_hp_rd_i.rresp[1:0]
x393_testbench01.simul_axi_hp_rd_i.rst[0]
x393_testbench01.simul_axi_hp_rd_i.rvalid[0]
@22
x393_testbench01.simul_axi_hp_rd_i.sim_rd_address[31:0]
x393_testbench01.simul_axi_hp_rd_i.sim_rd_cap[2:0]
x393_testbench01.simul_axi_hp_rd_i.sim_rd_data[63:0]
x393_testbench01.simul_axi_hp_rd_i.sim_rd_qos[3:0]
@28
x393_testbench01.simul_axi_hp_rd_i.sim_rd_ready[0]
@c00028
x393_testbench01.simul_axi_hp_rd_i.sim_rd_resp[1:0]
@28
(0)x393_testbench01.simul_axi_hp_rd_i.sim_rd_resp[1:0]
(1)x393_testbench01.simul_axi_hp_rd_i.sim_rd_resp[1:0]
@1401200
-group_end
@28
x393_testbench01.simul_axi_hp_rd_i.sim_rd_valid[0]
@22
x393_testbench01.simul_axi_hp_rd_i.sim_rid[5:0]
@28
x393_testbench01.simul_axi_hp_rd_i.start_read_burst_w[0]
x393_testbench01.simul_axi_hp_rd_i.was_addr_fifo_write[0]
x393_testbench01.simul_axi_hp_rd_i.was_data_fifo_read[0]
x393_testbench01.simul_axi_hp_rd_i.was_data_fifo_write[0]
@1401200
-simul_afi_rd
@c00200
-membridge
@28
x393_testbench01.x393_i.membridge_i.afi_rvalid[0]
x393_testbench01.x393_i.membridge_i.afi_rready[0]
x393_testbench01.x393_i.membridge_i.afi_rd_safe_not_empty[0]
@22
x393_testbench01.x393_i.membridge_i.afi_rcount[7:0]
@28
x393_testbench01.x393_i.membridge_i.bufwr_we_w[0]
@22
x393_testbench01.x393_i.membridge_i.bufwr_we[3:0]
@c00200
-x393_testbench01.x393_i.membridge_i.bufwr_we
@1401200
-group_end
@200
-
@28
x393_testbench01.x393_i.membridge_i.rdwr_en[0]
x393_testbench01.x393_i.membridge_i.read_busy[0]
x393_testbench01.x393_i.membridge_i.write_busy[0]
x393_testbench01.x393_i.membridge_i.busy[0]
x393_testbench01.x393_i.membridge_i.done[0]
@200
-
@22
x393_testbench01.x393_i.membridge_i.afi_awaddr[31:0]
x393_testbench01.x393_i.membridge_i.afi_awlen[3:0]
@28
x393_testbench01.x393_i.membridge_i.afi_awvalid[0]
x393_testbench01.x393_i.membridge_i.afi_wlast[0]
x393_testbench01.x393_i.membridge_i.afi_wvalid[0]
@200
-
@28
x393_testbench01.x393_i.membridge_i.read_over[0]
x393_testbench01.x393_i.membridge_i.read_started[0]
x393_testbench01.x393_i.membridge_i.left_zero[0]
@22
x393_testbench01.x393_i.membridge_i.axi_arw_requested[7:0]
x393_testbench01.x393_i.membridge_i.axi_bursts_requested[7:0]
x393_testbench01.x393_i.membridge_i.wresp_conf[7:0]
x393_testbench01.x393_i.membridge_i.axi_wr_pending[7:0]
@28
x393_testbench01.x393_i.membridge_i.read_busy[0]
@200
-
@22
x393_testbench01.x393_i.membridge_i.afi_arlen[3:0]
@28
x393_testbench01.x393_i.membridge_i.afi_arvalid[0]
x393_testbench01.x393_i.membridge_i.afi_rvalid[0]
x393_testbench01.x393_i.membridge_i.afi_rready[0]
@c00200
-x393_testbench01.x393_i.membridge_i.bufwr_we
@1401200
-group_end
@28
x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_we[0]
@c00022
x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]
@28
(0)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]
(1)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]
(2)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]
(3)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]
(4)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]
(5)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]
(6)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]
(7)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]
(8)x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_waddr[8:0]
@1401200
-group_end
@22
x393_testbench01.x393_i.membridge_i.chn1wr_buf_i.ext_data_in[63:0]
x393_testbench01.x393_i.membridge_i.afi_rdata[63:0]
x393_testbench01.x393_i.membridge_i.last_in_line64[13:0]
x393_testbench01.x393_i.membridge_i.buf_in_line64[13:0]
@28
x393_testbench01.x393_i.membridge_i.is_last_in_line[0]
x393_testbench01.x393_i.membridge_i.is_last_in_page[0]
@22
x393_testbench01.x393_i.membridge_i.left64[28:0]
@28
x393_testbench01.x393_i.membridge_i.page_ready[0]
x393_testbench01.x393_i.membridge_i.next_page[0]
@22
x393_testbench01.x393_i.membridge_i.afi_wacount[5:0]
x393_testbench01.x393_i.membridge_i.afi_wcount[7:0]
@28
x393_testbench01.x393_i.membridge_i.read_over[0]
x393_testbench01.x393_i.membridge_i.afi_awvalid[0]
x393_testbench01.simul_axi_hp_wr_i.awready[0]
x393_testbench01.simul_axi_hp_wr_i.awvalid[0]
x393_testbench01.simul_axi_hp_wr_i.aw_nempty[0]
x393_testbench01.simul_axi_hp_wr_i.wvalid[0]
x393_testbench01.x393_i.membridge_i.left_was_1[0]
@c00022
x393_testbench01.x393_i.membridge_i.src_wcntr[3:0]
@28
(0)x393_testbench01.x393_i.membridge_i.src_wcntr[3:0]
(1)x393_testbench01.x393_i.membridge_i.src_wcntr[3:0]
(2)x393_testbench01.x393_i.membridge_i.src_wcntr[3:0]
(3)x393_testbench01.x393_i.membridge_i.src_wcntr[3:0]
@1401200
-group_end
@28
x393_testbench01.x393_i.membridge_i.afi_wlast[0]
x393_testbench01.simul_axi_hp_wr_i.wlast[0]
@22
x393_testbench01.simul_axi_hp_wr_i.num_full_data[7:0]
@28
x393_testbench01.simul_axi_hp_wr_i.wdata_i.we[0]
x393_testbench01.simul_axi_hp_wr_i.wdata_i.re[0]
x393_testbench01.simul_axi_hp_wr_i.wready[0]
@22
x393_testbench01.simul_axi_hp_wr_i.wcount[7:0]
@28
x393_testbench01.simul_axi_hp_wr_i.enough_data[0]
x393_testbench01.simul_axi_hp_wr_i.start_write_burst_w[0]
@22
x393_testbench01.simul_axi_hp_wr_i.wacount[5:0]
@28
x393_testbench01.simul_axi_hp_wr_i.bvalid[0]
x393_testbench01.simul_axi_hp_wr_i.bready[0]
x393_testbench01.simul_axi_hp_wr_i.sim_wr_ready[0]
x393_testbench01.simul_axi_hp_wr_i.waddr_i.we[0]
x393_testbench01.simul_axi_hp_wr_i.waddr_i.re[0]
@22
x393_testbench01.simul_axi_hp_wr_i.waddr_i.num_in_fifo[5:0]
@200
-
@28
x393_testbench01.x393_i.membridge_i.read_busy[0]
x393_testbench01.x393_i.membridge_i.afi_wvalid[0]
x393_testbench01.simul_axi_hp_wr_i.fifo_wd_rd[0]
x393_testbench01.simul_axi_hp_wr_i.fifo_wd_rd_dly[0]
x393_testbench01.simul_axi_hp_wr_i.wresp_re[0]
x393_testbench01.x393_i.membridge_i.afi_bvalid[0]
x393_testbench01.x393_i.membridge_i.afi_bvalid_r[0]
@22
x393_testbench01.x393_i.membridge_i.axi_arw_requested[7:0]
x393_testbench01.x393_i.membridge_i.wresp_conf[7:0]
x393_testbench01.x393_i.membridge_i.axi_wr_pending[7:0]
@200
-
@28
x393_testbench01.x393_i.membridge_i.advance_rel_addr[0]
x393_testbench01.x393_i.membridge_i.advance_rel_addr_rd[0]
x393_testbench01.x393_i.membridge_i.advance_rel_addr_w[0]
x393_testbench01.x393_i.membridge_i.advance_rel_addr_wr[0]
@22
x393_testbench01.x393_i.membridge_i.afi_araddr[31:0]
@28
x393_testbench01.x393_i.membridge_i.afi_arburst[1:0]
@22
x393_testbench01.x393_i.membridge_i.afi_arcache[3:0]
x393_testbench01.x393_i.membridge_i.afi_arid[5:0]
x393_testbench01.x393_i.membridge_i.afi_arlen[3:0]
@28
x393_testbench01.x393_i.membridge_i.afi_arlock[1:0]
x393_testbench01.x393_i.membridge_i.afi_arprot[2:0]
@22
x393_testbench01.x393_i.membridge_i.afi_arqos[3:0]
@28
x393_testbench01.x393_i.membridge_i.afi_arready[0]
x393_testbench01.x393_i.membridge_i.afi_arvalid[0]
@22
x393_testbench01.x393_i.membridge_i.afi_awaddr[31:0]
@28
x393_testbench01.x393_i.membridge_i.afi_awburst[1:0]
@22
x393_testbench01.x393_i.membridge_i.afi_awcache[3:0]
x393_testbench01.x393_i.membridge_i.afi_awid[5:0]
x393_testbench01.x393_i.membridge_i.afi_awlen[3:0]
@28
x393_testbench01.x393_i.membridge_i.afi_awlock[1:0]
x393_testbench01.x393_i.membridge_i.afi_awprot[2:0]
@22
x393_testbench01.x393_i.membridge_i.afi_awqos[3:0]
@28
x393_testbench01.x393_i.membridge_i.afi_awready[0]
x393_testbench01.x393_i.membridge_i.afi_awvalid[0]
@22
x393_testbench01.x393_i.membridge_i.afi_bid[5:0]
@28
x393_testbench01.x393_i.membridge_i.afi_bready[0]
x393_testbench01.x393_i.membridge_i.afi_bresp[1:0]
x393_testbench01.x393_i.membridge_i.afi_bvalid[0]
x393_testbench01.x393_i.membridge_i.afi_bvalid_r[0]
@22
x393_testbench01.x393_i.membridge_i.afi_len[3:0]
x393_testbench01.x393_i.membridge_i.afi_len_plus1[4:0]
@28
x393_testbench01.x393_i.membridge_i.afi_ra_safe_not_full[0]
x393_testbench01.x393_i.membridge_i.afi_racount[2:0]
@22
x393_testbench01.x393_i.membridge_i.afi_rcount[7:0]
@28
x393_testbench01.x393_i.membridge_i.afi_rd_safe_not_empty[0]
@22
x393_testbench01.x393_i.membridge_i.afi_rdata[63:0]
@28
x393_testbench01.x393_i.membridge_i.afi_rdissuecap1en[0]
@22
x393_testbench01.x393_i.membridge_i.afi_rid[5:0]
@28
x393_testbench01.x393_i.membridge_i.afi_rlast[0]
x393_testbench01.x393_i.membridge_i.afi_rready[0]
x393_testbench01.x393_i.membridge_i.afi_rresp[1:0]
x393_testbench01.x393_i.membridge_i.afi_rvalid[0]
x393_testbench01.x393_i.membridge_i.afi_safe_rd_pending[0]
x393_testbench01.x393_i.membridge_i.afi_wa_safe_not_full[0]
@22
x393_testbench01.x393_i.membridge_i.afi_wacount[5:0]
x393_testbench01.x393_i.membridge_i.afi_wcount[7:0]
@28
x393_testbench01.x393_i.membridge_i.afi_wd_safe_not_full[0]
@22
x393_testbench01.x393_i.membridge_i.afi_wdata[63:0]
x393_testbench01.x393_i.membridge_i.afi_wid[5:0]
@28
x393_testbench01.x393_i.membridge_i.afi_wlast[0]
x393_testbench01.x393_i.membridge_i.afi_wready[0]
x393_testbench01.x393_i.membridge_i.afi_wrissuecap1en[0]
@22
x393_testbench01.x393_i.membridge_i.afi_wstrb[7:0]
@28
x393_testbench01.x393_i.membridge_i.afi_wvalid[0]
@22
x393_testbench01.x393_i.membridge_i.axi_addr64[28:0]
x393_testbench01.x393_i.membridge_i.axi_arw_requested[7:0]
x393_testbench01.x393_i.membridge_i.axi_bursts_requested[7:0]
x393_testbench01.x393_i.membridge_i.axi_rd_pending[7:0]
x393_testbench01.x393_i.membridge_i.axi_rd_received[7:0]
x393_testbench01.x393_i.membridge_i.buf_in_line64[13:0]
x393_testbench01.x393_i.membridge_i.buf_in_line64_r[6:0]
x393_testbench01.x393_i.membridge_i.buf_left64[28:0]
@28
x393_testbench01.x393_i.membridge_i.buf_rd[0]
@22
x393_testbench01.x393_i.membridge_i.buf_rdata[63:0]
@28
x393_testbench01.x393_i.membridge_i.buf_rdwr[0]
x393_testbench01.x393_i.membridge_i.buf_rpage_nxt[0]
@22
x393_testbench01.x393_i.membridge_i.buf_wdata[63:0]
@28
x393_testbench01.x393_i.membridge_i.buf_wpage_nxt[0]
x393_testbench01.x393_i.membridge_i.buf_wr[0]
x393_testbench01.x393_i.membridge_i.bufrd_rd[2:0]
x393_testbench01.x393_i.membridge_i.bufrd_rd_w[0]
@800200
-x393_testbench01.x393_i.membridge_i.bufwr_we
@1001200
-group_end
@28
x393_testbench01.x393_i.membridge_i.bufwr_we_w[0]
x393_testbench01.x393_i.membridge_i.busy[0]
x393_testbench01.x393_i.membridge_i.busy_next_page[0]
@22
x393_testbench01.x393_i.membridge_i.cmd_a[3:0]
x393_testbench01.x393_i.membridge_i.cmd_ad[7:0]
x393_testbench01.x393_i.membridge_i.cmd_data[31:0]
@28
x393_testbench01.x393_i.membridge_i.cmd_stb[0]
x393_testbench01.x393_i.membridge_i.cmd_we[0]
x393_testbench01.x393_i.membridge_i.cmd_wrmem[0]
x393_testbench01.x393_i.membridge_i.done[0]
@22
x393_testbench01.x393_i.membridge_i.frame_done[0]
@28
x393_testbench01.x393_i.membridge_i.frame_done_chn[0]
x393_testbench01.x393_i.membridge_i.frame_start_chn[0]
x393_testbench01.x393_i.membridge_i.hclk[0]
x393_testbench01.x393_i.membridge_i.is_last_in_line[0]
x393_testbench01.x393_i.membridge_i.is_last_in_page[0]
@22
x393_testbench01.x393_i.membridge_i.last_addr1k[24:0]
@28
x393_testbench01.x393_i.membridge_i.last_burst[0]
@22
x393_testbench01.x393_i.membridge_i.last_in_line64[13:0]
x393_testbench01.x393_i.membridge_i.left64[28:0]
@28
x393_testbench01.x393_i.membridge_i.left_was_1[0]
x393_testbench01.x393_i.membridge_i.left_zero[0]
@22
x393_testbench01.x393_i.membridge_i.len64[28:0]
x393_testbench01.x393_i.membridge_i.len64_mclk[28:0]
x393_testbench01.x393_i.membridge_i.line_unfinished_chn1[15:0]
x393_testbench01.x393_i.membridge_i.lo_addr64[28:0]
x393_testbench01.x393_i.membridge_i.lo_addr64_mclk[28:0]
@28
x393_testbench01.x393_i.membridge_i.low4_zero[0]
x393_testbench01.x393_i.membridge_i.mclk[0]
x393_testbench01.x393_i.membridge_i.next_page[0]
x393_testbench01.x393_i.membridge_i.next_page_chn[0]
x393_testbench01.x393_i.membridge_i.next_page_rd[0]
x393_testbench01.x393_i.membridge_i.next_page_rd_w[0]
x393_testbench01.x393_i.membridge_i.next_page_wr[0]
x393_testbench01.x393_i.membridge_i.next_page_wr_w[0]
x393_testbench01.x393_i.membridge_i.page_ready[0]
x393_testbench01.x393_i.membridge_i.page_ready_chn[0]
x393_testbench01.x393_i.membridge_i.page_ready_rd[0]
x393_testbench01.x393_i.membridge_i.page_ready_wr[0]
@22
x393_testbench01.x393_i.membridge_i.rd_id[4:0]
@28
x393_testbench01.x393_i.membridge_i.rd_start[0]
x393_testbench01.x393_i.membridge_i.rdwr_en[0]
x393_testbench01.x393_i.membridge_i.rdwr_en_mclk[0]
x393_testbench01.x393_i.membridge_i.rdwr_reset_addr[0]
x393_testbench01.x393_i.membridge_i.rdwr_reset_addr_mclk[0]
x393_testbench01.x393_i.membridge_i.rdwr_start[2:0]
x393_testbench01.x393_i.membridge_i.read_busy[0]
x393_testbench01.x393_i.membridge_i.read_over[0]
@22
x393_testbench01.x393_i.membridge_i.read_page[1:0]
x393_testbench01.x393_i.membridge_i.read_pages_ready[2:0]
@28
x393_testbench01.x393_i.membridge_i.read_started[0]
@22
x393_testbench01.x393_i.membridge_i.rel_addr64[28:0]
@28
x393_testbench01.x393_i.membridge_i.reset_page_rd[0]
x393_testbench01.x393_i.membridge_i.reset_page_wr[0]
x393_testbench01.x393_i.membridge_i.rollover[0]
x393_testbench01.x393_i.membridge_i.rw_in_progress[0]
x393_testbench01.x393_i.membridge_i.set_ctrl_w[0]
x393_testbench01.x393_i.membridge_i.set_len64_w[0]
x393_testbench01.x393_i.membridge_i.set_lo_addr64_w[0]
x393_testbench01.x393_i.membridge_i.set_size64_w[0]
x393_testbench01.x393_i.membridge_i.set_start64_w[0]
x393_testbench01.x393_i.membridge_i.set_status_w[0]
x393_testbench01.x393_i.membridge_i.set_width64_w[0]
@22
x393_testbench01.x393_i.membridge_i.size64[28:0]
x393_testbench01.x393_i.membridge_i.size64_mclk[28:0]
x393_testbench01.x393_i.membridge_i.src_wcntr[3:0]
x393_testbench01.x393_i.membridge_i.start64[28:0]
x393_testbench01.x393_i.membridge_i.start64_mclk[28:0]
@28
x393_testbench01.x393_i.membridge_i.start_hclk[0]
x393_testbench01.x393_i.membridge_i.start_mclk[0]
@22
x393_testbench01.x393_i.membridge_i.status_ad[7:0]
@28
x393_testbench01.x393_i.membridge_i.status_rq[0]
x393_testbench01.x393_i.membridge_i.status_start[0]
x393_testbench01.x393_i.membridge_i.suspend_chn1[0]
@22
x393_testbench01.x393_i.membridge_i.wr_id[4:0]
@28
x393_testbench01.x393_i.membridge_i.wr_mode[0]
x393_testbench01.x393_i.membridge_i.wr_start[0]
@c00200
-x393_testbench01.x393_i.membridge_i.wresp_pending
@1401200
-group_end
@28
x393_testbench01.x393_i.membridge_i.write_busy[0]
x393_testbench01.x393_i.membridge_i.write_page[1:0]
x393_testbench01.x393_i.membridge_i.write_page_r[1:0]
x393_testbench01.x393_i.membridge_i.write_pages_ready[2:0]
x393_testbench01.x393_i.membridge_i.xfer_reset_page_rd[0]
x393_testbench01.x393_i.membridge_i.xfer_reset_page_wr[0]
@200
-
@28
x393_testbench01.x393_i.membridge_i.cmd_we[0]
x393_testbench01.x393_i.membridge_i.set_status_w[0]
@c00200
-membridge_status
@22
x393_testbench01.x393_i.membridge_i.status_generate_i.ad[7:0]
@28
x393_testbench01.x393_i.membridge_i.status_generate_i.clk[0]
x393_testbench01.x393_i.membridge_i.status_generate_i.rq[0]
x393_testbench01.x393_i.membridge_i.status_generate_i.rst[0]
x393_testbench01.x393_i.membridge_i.status_generate_i.start[0]
@22
x393_testbench01.x393_i.membridge_i.status_generate_i.wd[7:0]
@28
x393_testbench01.x393_i.membridge_i.status_generate_i.we[0]
@1401200
-membridge_status
-membridge
@c00200
-debug_01
@28
x393_testbench01.enable_memcntrl.en[0]
@22
x393_testbench01.axi_set_wbuf_delay.delay[3:0]
x393_testbench01.read_status.address[7:0]
x393_testbench01.read_and_wait_w.address[29:0]
x393_testbench01.read_and_wait.address[31:0]
@800200
-axi_read_addr
@22
x393_testbench01.axi_read_addr.addr[31:0]
@28
x393_testbench01.axi_read_addr.burst[1:0]
@22
x393_testbench01.axi_read_addr.id[11:0]
x393_testbench01.axi_read_addr.len[3:0]
@28
x393_testbench01.AR_SET_CMD[0]
@1000200
-axi_read_addr
@28
x393_testbench01.rvalid[0]
x393_testbench01.rready[0]
x393_testbench01.enable_cmda.en[0]
@1401200
-debug_01
@800200
-debug_o2
@28
x393_testbench01.x393_i.mclk[0]
@c00200
-cmd0_buf
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.data_in[31:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.data_out[31:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.raddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.rclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.ren[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.waddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.wclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.we[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.web[3:0]
@1401200
-cmd0_buf
@200
-
@800200
-mcntrl16_sel
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mrst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_0bit_we[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_0bit_addr[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_en[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_reset[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_enabled[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_fill[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_full[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_need[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_set[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.cmd_seq_run[0]
@1000200
-mcntrl16_sel
@c00200
-sheduler16
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.chn_en[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.en_schedul[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_chn[3:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_chn_r[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_r[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_sent[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_w[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.index[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.index_valid[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.mrst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_conf[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_r2[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_r[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_rq[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_set[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_some[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_want_conf[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_want_conf_d[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.need_want_conf_w[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.next_need_conf[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.next_want_conf[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_addr[3:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_data[15:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pgm_en[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.pri_reg[255:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.sched_state[255:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_conf[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_need_set_r[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_rq[15:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_set[15:0]
@1401200
-sheduler16
@c00200
-mcontr_common_chnbuf_reg0
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.buf_chn_sel[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.buf_done[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.buf_run[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.ext_buf_page_nxt[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.ext_buf_rchn[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.ext_buf_rrefresh[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.ext_buf_run[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.page_nxt[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_common_chnbuf_reg0_i.seq_done[0]
@1401200
-mcontr_common_chnbuf_reg0
@22
x393_testbench01.set_mrs.cmd_addr[29:0]
x393_testbench01.set_mrs.data[31:0]
x393_testbench01.set_mrs.mr0[17:0]
x393_testbench01.set_mrs.mr1[17:0]
x393_testbench01.set_mrs.mr2[17:0]
x393_testbench01.set_mrs.mr3[17:0]
@28
x393_testbench01.set_mrs.reset_dll[0]
@200
-
@1000200
-debug_o2
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mrst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.dly_rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.rst[0]
x393_testbench01.x393_i.idelay_ctrl_reset[0]
x393_testbench01.x393_i.idelay_ctrl_rdy[0]
@200
-
@28
x393_testbench01.x393_i.mrst[0]
@800200
-sync_resets
@28
x393_testbench01.x393_i.sync_resets_i.arst[0]
@c00022
x393_testbench01.x393_i.sync_resets_i.clk[6:0]
@28
(0)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
(1)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
(2)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
(3)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
(4)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
(5)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
(6)x393_testbench01.x393_i.sync_resets_i.clk[6:0]
@1401200
-group_end
@800022
x393_testbench01.x393_i.sync_resets_i.locked[6:0]
@28
(0)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
(1)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
(2)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
(3)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
(4)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
(5)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
(6)x393_testbench01.x393_i.sync_resets_i.locked[6:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.sync_resets_i.mrst[0]
@800022
x393_testbench01.x393_i.sync_resets_i.rst[6:0]
@28
(0)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
(1)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
(2)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
(3)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
(4)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
(5)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
(6)x393_testbench01.x393_i.sync_resets_i.rst[6:0]
@1001200
-group_end
@28
x393_testbench01.x393_i.sync_resets_i.rst_early_master[0]
@22
x393_testbench01.x393_i.sync_resets_i.rst_w[6:0]
@200
-
@28
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.clk[0]
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.d_in[0]
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.d_out[0]
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.d_sync[0]
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.regs[1:0]
@200
-
@c00200
-level_cross_clocks_sync_bit
@28
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.level_cross_clocks_sync_bit_i.clk[0]
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.level_cross_clocks_sync_bit_i.d_in[0]
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.level_cross_clocks_sync_bit_i.d_out[0]
x393_testbench01.x393_i.sync_resets_i.level_cross_clocks_mrst_i.level_cross_clock_block[0].genblk5.level_cross_clocks_single_i.level_cross_clocks_sync_bit_i.sync_zer[1:0]
@1401200
-level_cross_clocks_sync_bit
@1000200
-sync_resets
@c00200
-clocks393
@28
x393_testbench01.x393_i.clocks393_i.aclk[0]
x393_testbench01.x393_i.clocks393_i.async_rst[0]
x393_testbench01.x393_i.clocks393_i.cmd_a[0]
@22
x393_testbench01.x393_i.clocks393_i.cmd_ad[7:0]
x393_testbench01.x393_i.clocks393_i.cmd_data[10:0]
@28
x393_testbench01.x393_i.clocks393_i.cmd_stb[0]
x393_testbench01.x393_i.clocks393_i.cmd_we[0]
x393_testbench01.x393_i.clocks393_i.extra_status[1:0]
@22
x393_testbench01.x393_i.clocks393_i.fclk[3:0]
@28
x393_testbench01.x393_i.clocks393_i.ffclk0[0]
x393_testbench01.x393_i.clocks393_i.ffclk0_rst[0]
x393_testbench01.x393_i.clocks393_i.ffclk0n_pad[0]
x393_testbench01.x393_i.clocks393_i.ffclk0p_pad[0]
x393_testbench01.x393_i.clocks393_i.ffclk1[0]
x393_testbench01.x393_i.clocks393_i.ffclk1_rst[0]
x393_testbench01.x393_i.clocks393_i.ffclk1n_pad[0]
x393_testbench01.x393_i.clocks393_i.ffclk1p_pad[0]
x393_testbench01.x393_i.clocks393_i.hclk[0]
@22
x393_testbench01.x393_i.clocks393_i.locked[3:0]
@28
x393_testbench01.x393_i.clocks393_i.locked_hclk[0]
x393_testbench01.x393_i.clocks393_i.locked_pclk[0]
x393_testbench01.x393_i.clocks393_i.locked_sync_clk[0]
x393_testbench01.x393_i.clocks393_i.locked_xclk[0]
x393_testbench01.x393_i.clocks393_i.mclk[0]
x393_testbench01.x393_i.clocks393_i.memclk[0]
x393_testbench01.x393_i.clocks393_i.memclk_pad[0]
x393_testbench01.x393_i.clocks393_i.memclk_rst[0]
x393_testbench01.x393_i.clocks393_i.mrst[0]
x393_testbench01.x393_i.clocks393_i.pclk2x[0]
x393_testbench01.x393_i.clocks393_i.pclk[0]
@22
x393_testbench01.x393_i.clocks393_i.pwrdwn_clk[3:0]
x393_testbench01.x393_i.clocks393_i.reset_clk[6:0]
@28
x393_testbench01.x393_i.clocks393_i.set_ctrl_w[0]
x393_testbench01.x393_i.clocks393_i.set_status_w[0]
@22
x393_testbench01.x393_i.clocks393_i.status_ad[7:0]
x393_testbench01.x393_i.clocks393_i.status_data[8:0]
@28
x393_testbench01.x393_i.clocks393_i.status_rq[0]
x393_testbench01.x393_i.clocks393_i.status_start[0]
x393_testbench01.x393_i.clocks393_i.sync_clk[0]
x393_testbench01.x393_i.clocks393_i.test_clk[2:0]
x393_testbench01.x393_i.clocks393_i.time_ref[0]
x393_testbench01.x393_i.clocks393_i.time_ref_r[2:0]
x393_testbench01.x393_i.clocks393_i.xclk2x[0]
x393_testbench01.x393_i.clocks393_i.xclk[0]
@1401200
-clocks393
@22
x393_testbench01.x393_i.membridge_i.status_generate_i.status[17:0]
@28
x393_testbench01.x393_i.membridge_i.status_generate_i.rq[0]
x393_testbench01.x393_i.membridge_i.status_generate_i.start[0]
@22
x393_testbench01.x393_i.membridge_i.status_generate_i.ad[7:0]
@c00200
-wait_stat_cond
@28
x393_testbench01.wait_status_condition.invert_match[0]
@22
x393_testbench01.wait_status_condition.mask[25:0]
@28
x393_testbench01.wait_status_condition.match[0]
@22
x393_testbench01.wait_status_condition.pattern[25:0]
x393_testbench01.wait_status_condition.seq_num[5:0]