Merge pull request #19 from zhipengzhaocmu/main

Add external loopback test

debug/board_bring_up/external_loopback/.gitignore

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+ethernet
+quartus_project
+hw_test/hwtest

debug/board_bring_up/external_loopback/README.md

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+# External Loopback Test
+This project tests the external loopback of the two 100Gbps Ethernet ports of Intel Stratix-10 MX dev kit. An external 100G cable is needed to wire the two QSFP ports of the board. This project only contains two 100Gbps MAC IPs without any packet processing logic. 
+
+1. Generate bitstream
+```bash
+./run_quartus
+```
+
+2. Load the bitstream to the Intel MX development kit.
+```bash
+cd hw_test
+./load_bitstream.sh
+```
+
+3. Send packet from one port (using port 0 in this example).
+Once the system finishes booting, run the JTAG system console with:
+```bash
+./run_console.sh
+```
+After the console starts, run:
+```
+source path.tcl
+```
+> It may return some error the first time. Exit it using Ctrl-C. Then relaunch the console (`./run_console`) and rerun `source path.tcl.
+In the tcl console, you will need to type some tcl commands.
+Check the initial value, should be all zero
+```
+chkmac_stats
+```
+Send pkt
+```
+start_pkt_gen
+stop_pkt_gen
+```
+Check the value again, the TX part should return non-zero values, indicating number of packets of different sizes. RX is zero
+```
+chkmac_stats
+```
+Ctrl-C to exit
+
+4. Check results of the other port
+```
+cd hwtest/altera/sval_top
+```
+Comment Port 0 and uncomment Port 1 (assuming step 2 is using port 0)
+```
+vi reg_map_inc.tcl
+```
+The RX part value should match with the TX of the sending port. 
+```
+cd ../../../
+./run_console.sh
+source path.tcl
+chkmac_stats
+```

debug/board_bring_up/external_loopback/eth.tcl

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+package require -exact qsys 18.0
+
+# create the system "ip_gen_alt_ehipc2_0"
+proc do_create_ip_gen_alt_ehipc2_0 {} {
+	# create the system
+	create_system ip_gen_alt_ehipc2_0
+	set_project_property DEVICE {1SM21BHU2F53E1VG}
+	set_project_property DEVICE_FAMILY {Stratix 10}
+	set_project_property HIDE_FROM_IP_CATALOG {false}
+	set_use_testbench_naming_pattern 0 {}
+
+	# add the components
+	add_instance alt_ehipc2_0 alt_ehipc2 19.2.0
+	set_instance_parameter_value alt_ehipc2_0 {AN_CHAN} {1}
+	set_instance_parameter_value alt_ehipc2_0 {AN_CR} {1}
+	set_instance_parameter_value alt_ehipc2_0 {AN_PAUSE_C0} {1}
+	set_instance_parameter_value alt_ehipc2_0 {AN_PAUSE_C1} {1}
+	set_instance_parameter_value alt_ehipc2_0 {CASCADE_ATX_PLL} {1}
+	set_instance_parameter_value alt_ehipc2_0 {CL72_PRBS} {0}
+	set_instance_parameter_value alt_ehipc2_0 {DEV_BOARD} {1}
+	set_instance_parameter_value alt_ehipc2_0 {ENABLE_ADME} {0}
+	set_instance_parameter_value alt_ehipc2_0 {ENABLE_ANLT} {0}
+	set_instance_parameter_value alt_ehipc2_0 {ENABLE_ASYNC_ADAPTERS} {0}
+	set_instance_parameter_value alt_ehipc2_0 {ENABLE_JTAG_AVMM} {0}
+	set_instance_parameter_value alt_ehipc2_0 {EXAMPLE_DESIGN} {1}
+	set_instance_parameter_value alt_ehipc2_0 {GEN_SIM} {0}
+	set_instance_parameter_value alt_ehipc2_0 {GEN_SYNTH} {1}
+	set_instance_parameter_value alt_ehipc2_0 {HDL_FORMAT} {1}
+	set_instance_parameter_value alt_ehipc2_0 {HW_DEVICE} {1}
+	set_instance_parameter_value alt_ehipc2_0 {INITMAINVAL} {25}
+	set_instance_parameter_value alt_ehipc2_0 {INITPOSTVAL} {13}
+	set_instance_parameter_value alt_ehipc2_0 {INITPREVAL} {3}
+	set_instance_parameter_value alt_ehipc2_0 {LINK_TIMER_KR} {504}
+	set_instance_parameter_value alt_ehipc2_0 {PHY_ANALOG_VOLTAGE} {1_1V}
+	set_instance_parameter_value alt_ehipc2_0 {PHY_REFCLK} {644.53125}
+	set_instance_parameter_value alt_ehipc2_0 {PREMAINVAL} {30}
+	set_instance_parameter_value alt_ehipc2_0 {PREPOSTVAL} {0}
+	set_instance_parameter_value alt_ehipc2_0 {PREPREVAL} {0}
+	set_instance_parameter_value alt_ehipc2_0 {STATUS_CLK_MHZ} {100.0}
+	set_instance_parameter_value alt_ehipc2_0 {SYNTH_AN} {1}
+	set_instance_parameter_value alt_ehipc2_0 {SYNTH_LT} {1}
+	set_instance_parameter_value alt_ehipc2_0 {TRNWTWIDTH_gui} {127}
+	set_instance_parameter_value alt_ehipc2_0 {USE_DEBUG_CPU} {0}
+	set_instance_parameter_value alt_ehipc2_0 {VMAXRULE} {30}
+	set_instance_parameter_value alt_ehipc2_0 {VMINRULE} {6}
+	set_instance_parameter_value alt_ehipc2_0 {VODMINRULE} {14}
+	set_instance_parameter_value alt_ehipc2_0 {VPOSTRULE} {25}
+	set_instance_parameter_value alt_ehipc2_0 {VPRERULE} {16}
+	set_instance_parameter_value alt_ehipc2_0 {additional_ipg_removed} {0}
+	set_instance_parameter_value alt_ehipc2_0 {avmm_test} {0}
+	set_instance_parameter_value alt_ehipc2_0 {duplex_mode} {enable}
+	set_instance_parameter_value alt_ehipc2_0 {ehip_mode_gui} {MAC+PCS}
+	set_instance_parameter_value alt_ehipc2_0 {ehip_rate_gui} {100G}
+	set_instance_parameter_value alt_ehipc2_0 {enforce_max_frame_size_gui} {0}
+	set_instance_parameter_value alt_ehipc2_0 {flow_control_gui} {No}
+	set_instance_parameter_value alt_ehipc2_0 {forward_rx_pause_requests_gui} {0}
+	set_instance_parameter_value alt_ehipc2_0 {link_fault_mode_gui} {OFF}
+	set_instance_parameter_value alt_ehipc2_0 {preamble_passthrough_gui} {0}
+	set_instance_parameter_value alt_ehipc2_0 {ready_latency} {0}
+	set_instance_parameter_value alt_ehipc2_0 {rx_bytes_to_remove} {Remove CRC bytes}
+	set_instance_parameter_value alt_ehipc2_0 {rx_max_frame_size_gui} {1518}
+	set_instance_parameter_value alt_ehipc2_0 {rx_vlan_detection_gui} {1}
+	set_instance_parameter_value alt_ehipc2_0 {source_address_insertion_gui} {0}
+	set_instance_parameter_value alt_ehipc2_0 {strict_preamble_checking_gui} {0}
+	set_instance_parameter_value alt_ehipc2_0 {strict_sfd_checking_gui} {0}
+	set_instance_parameter_value alt_ehipc2_0 {tx_ipg_size_gui} {12}
+	set_instance_parameter_value alt_ehipc2_0 {tx_max_frame_size_gui} {1518}
+	set_instance_parameter_value alt_ehipc2_0 {tx_vlan_detection_gui} {1}
+	set_instance_parameter_value alt_ehipc2_0 {txmac_saddr_gui} {73588229205}
+	set_instance_property alt_ehipc2_0 AUTO_EXPORT true
+
+	# add wirelevel expressions
+
+	# add the exports
+	set_interface_property i_stats_snapshot EXPORT_OF alt_ehipc2_0.i_stats_snapshot
+	set_interface_property o_cdr_lock EXPORT_OF alt_ehipc2_0.o_cdr_lock
+	set_interface_property i_eth_reconfig_addr EXPORT_OF alt_ehipc2_0.i_eth_reconfig_addr
+	set_interface_property i_eth_reconfig_read EXPORT_OF alt_ehipc2_0.i_eth_reconfig_read
+	set_interface_property i_eth_reconfig_write EXPORT_OF alt_ehipc2_0.i_eth_reconfig_write
+	set_interface_property o_eth_reconfig_readdata EXPORT_OF alt_ehipc2_0.o_eth_reconfig_readdata
+	set_interface_property o_eth_reconfig_readdata_valid EXPORT_OF alt_ehipc2_0.o_eth_reconfig_readdata_valid
+	set_interface_property i_eth_reconfig_writedata EXPORT_OF alt_ehipc2_0.i_eth_reconfig_writedata
+	set_interface_property o_eth_reconfig_waitrequest EXPORT_OF alt_ehipc2_0.o_eth_reconfig_waitrequest
+	set_interface_property o_tx_lanes_stable EXPORT_OF alt_ehipc2_0.o_tx_lanes_stable
+	set_interface_property o_rx_pcs_ready EXPORT_OF alt_ehipc2_0.o_rx_pcs_ready
+	set_interface_property o_ehip_ready EXPORT_OF alt_ehipc2_0.o_ehip_ready
+	set_interface_property o_rx_block_lock EXPORT_OF alt_ehipc2_0.o_rx_block_lock
+	set_interface_property o_rx_am_lock EXPORT_OF alt_ehipc2_0.o_rx_am_lock
+	set_interface_property o_rx_hi_ber EXPORT_OF alt_ehipc2_0.o_rx_hi_ber
+	set_interface_property i_tx_pll_locked EXPORT_OF alt_ehipc2_0.i_tx_pll_locked
+	set_interface_property o_local_fault_status EXPORT_OF alt_ehipc2_0.o_local_fault_status
+	set_interface_property o_remote_fault_status EXPORT_OF alt_ehipc2_0.o_remote_fault_status
+	set_interface_property i_clk_ref EXPORT_OF alt_ehipc2_0.i_clk_ref
+	set_interface_property i_clk_tx EXPORT_OF alt_ehipc2_0.i_clk_tx
+	set_interface_property i_clk_rx EXPORT_OF alt_ehipc2_0.i_clk_rx
+	set_interface_property o_clk_pll_div64 EXPORT_OF alt_ehipc2_0.o_clk_pll_div64
+	set_interface_property o_clk_pll_div66 EXPORT_OF alt_ehipc2_0.o_clk_pll_div66
+	set_interface_property o_clk_rec_div64 EXPORT_OF alt_ehipc2_0.o_clk_rec_div64
+	set_interface_property o_clk_rec_div66 EXPORT_OF alt_ehipc2_0.o_clk_rec_div66
+	set_interface_property i_tx_serial_clk EXPORT_OF alt_ehipc2_0.i_tx_serial_clk
+	set_interface_property i_csr_rst_n EXPORT_OF alt_ehipc2_0.i_csr_rst_n
+	set_interface_property i_tx_rst_n EXPORT_OF alt_ehipc2_0.i_tx_rst_n
+	set_interface_property i_rx_rst_n EXPORT_OF alt_ehipc2_0.i_rx_rst_n
+	set_interface_property o_tx_serial EXPORT_OF alt_ehipc2_0.o_tx_serial
+	set_interface_property i_rx_serial EXPORT_OF alt_ehipc2_0.i_rx_serial
+	set_interface_property i_reconfig_clk EXPORT_OF alt_ehipc2_0.i_reconfig_clk
+	set_interface_property i_reconfig_reset EXPORT_OF alt_ehipc2_0.i_reconfig_reset
+	set_interface_property i_xcvr_reconfig_address EXPORT_OF alt_ehipc2_0.i_xcvr_reconfig_address
+	set_interface_property i_xcvr_reconfig_read EXPORT_OF alt_ehipc2_0.i_xcvr_reconfig_read
+	set_interface_property i_xcvr_reconfig_write EXPORT_OF alt_ehipc2_0.i_xcvr_reconfig_write
+	set_interface_property o_xcvr_reconfig_readdata EXPORT_OF alt_ehipc2_0.o_xcvr_reconfig_readdata
+	set_interface_property i_xcvr_reconfig_writedata EXPORT_OF alt_ehipc2_0.i_xcvr_reconfig_writedata
+	set_interface_property o_xcvr_reconfig_waitrequest EXPORT_OF alt_ehipc2_0.o_xcvr_reconfig_waitrequest
+	set_interface_property nonpcs_ports EXPORT_OF alt_ehipc2_0.nonpcs_ports
+	set_interface_property pfc_ports EXPORT_OF alt_ehipc2_0.pfc_ports
+	set_interface_property pause_ports EXPORT_OF alt_ehipc2_0.pause_ports
+
+	# set the the module properties
+	set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?>
+<bonusData>
+ <element __value="alt_ehipc2_0">
+  <datum __value="_sortIndex" value="0" type="int" />
+ </element>
+</bonusData>
+}
+	set_module_property FILE {ip_gen_alt_ehipc2_0.ip}
+	set_module_property GENERATION_ID {0x00000000}
+	set_module_property NAME {ip_gen_alt_ehipc2_0}
+
+	# save the system
+	sync_sysinfo_parameters
+	save_system ip_gen_alt_ehipc2_0
+}
+
+# create all the systems, from bottom up
+do_create_ip_gen_alt_ehipc2_0

debug/board_bring_up/external_loopback/hw_test/.gitignore

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+*.sof

debug/board_bring_up/external_loopback/hw_test/load.cdf

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+/* Quartus Prime Version 19.3.0 Build 222 09/23/2019 SC Pro Edition */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(1SM21BHU2F53S1) Path("./") File("alt_ehipc2_hw.sof") MfrSpec(OpMask(1));
+	P ActionCode(Ign)
+		Device PartName(VTAP10) MfrSpec(OpMask(0));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;

debug/board_bring_up/external_loopback/hw_test/load_bitstream.sh

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+#copy from the quartus project
+cp ../quartus_project/hardware_test_desgin/output_files/alt_ehipc2_hw.sof ./
+
+quartus_pgm -c Intel\ Stratix\ 10\ MX\ FPGA\ Development\ Kit\ [1-12] ./load.cdf 

debug/board_bring_up/external_loopback/hw_test/path.tcl

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+cd ./hwtest/
+source main.tcl

debug/board_bring_up/external_loopback/hw_test/run_console.sh

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+system-console -cli

debug/board_bring_up/external_loopback/manipulate_tcl.py

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+#! /usr/bin/env python3
+
+import sys
+
+def change_tcl(fname):
+    new_file = []
+    first = 1
+    f = open(fname,'r')
+    for line in f:
+        if ("set" in line) and first:
+            new_line = "#Port 0 Eth \n"
+            new_file.append(new_line)
+            first = 0
+
+        if ("BASE_TRFC" in line):
+            new_line = " set BASE_TRFC \t 0x04001000 \n"
+            new_file.append(new_line)
+        else:
+            new_file.append(line)
+
+        if ("RECO_CH" in line):
+            new_file.append("#Port 1 Eth \n")
+            new_file.append("#set BASE_KR4         0x02000000 \n")
+            new_file.append("#set BASE_RXPHY       0x02000300 \n")
+            new_file.append("#set BASE_TXMAC       0x02000400 \n")
+            new_file.append("#set BASE_RXMAC       0x02000500 \n")
+            new_file.append("#set BASE_TXSTATS     0x02000800 \n")
+            new_file.append("#set BASE_RXSTATS     0x02000900 \n")
+            new_file.append("#set BASE_TRFC        0x02001000 \n")
+            new_file.append("#set BASE_PMDC        0x02002000 \n")
+            new_file.append("#set BASE_S10RECO     0x02010000 \n")
+            new_file.append("#set RECO_CH          0x02001000 \n")
+    f.close()
+
+    with open(fname, 'w') as f:
+        for line in new_file:
+            f.write("%s" % line)
+
+if __name__ == "__main__":
+    fname = sys.argv[1]
+
+    change_tcl(fname)
+

debug/board_bring_up/external_loopback/run_ipgen.sh

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+#! /usr/bin/env sh
+
+#Clean old data
+rm -f ip_gen.qsf
+rm -f ip_gen.qpf
+rm -f ip_gen.qsys
+rm -rf ip_gen
+rm -rf qdb
+rm -rf ip
+
+#Generate Ethernet
+rm -rf ethernet
+mkdir ethernet
+cp eth.tcl ethernet/
+cd ethernet
+qsys-script --script=eth.tcl
+#generate example design
+qsys-generate ip_gen_alt_ehipc2_0.ip -example-design
+cd ip_gen_alt_ehipc2_0_example_design/alt_ehipc2_0_example_design/hardware_test_design/common/
+qsys-generate reset_ip.ip --synthesis=VERILOG --part=1SM21BHU2F53E1VG 
+qsys-generate alt_ehipc2_jtag_avalon.ip --synthesis=VERILOG --part=1SM21BHU2F53E1VG 
+qsys-generate alt_ehipc2_sys_pll.ip --synthesis=VERILOG --part=1SM21BHU2F53E1VG
+qsys-generate probe8.ip --synthesis=VERILOG --part=1SM21BHU2F53E1VG 
+qsys-generate reset_ip.ip --synthesis=VERILOG --part=1SM21BHU2F53E1VG 
+cd ../../../../../

debug/board_bring_up/external_loopback/run_quartus.sh

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+#! /usr/bin/env sh
+
+./run_ipgen.sh
+./run_quartus_create.sh
+./run_quartus_synth.sh

debug/board_bring_up/external_loopback/run_quartus_create.sh

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+#! /usr/bin/env sh
+
+rm -rf quartus_project
+mkdir quartus_project
+
+
+#Copy Ethernet example design
+cp -r ./ethernet/ip_gen_alt_ehipc2_0_example_design/alt_ehipc2_0_example_design/hardware_test_design ./quartus_project/
+cp -r ./ethernet/ip_gen_alt_ehipc2_0_example_design/alt_ehipc2_0_example_design/ex_100G ./quartus_project/
+cp ./ethernet/ip_gen_alt_ehipc2_0_example_design/alt_ehipc2_0_example_design/ex_100G.ip ./quartus_project/
+
+#Replace the quartus files
+rm ./quartus_project/hardware_test_design/alt_ehipc2_hw.qsf
+rm ./quartus_project/hardware_test_design/alt_ehipc2_hw.sdc
+rm ./quartus_project/hardware_test_design/alt_ehipc2_hw.v
+cp src/alt_ehipc2_hw.* ./quartus_project/hardware_test_design/
+
+
+# copy hwtest
+if [ -d "./hw_test/hwtest/" ]
+then
+    rm -r ./hw_test/hwtest/
+fi
+cp -r ./ethernet/ip_gen_alt_ehipc2_0_example_design/alt_ehipc2_0_example_design/hardware_test_design/hwtest ./hw_test/
+./manipulate_tcl.py ./hw_test/hwtest/altera/sval_top/reg_map_inc.tcl

debug/board_bring_up/external_loopback/run_quartus_synth.sh

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+#!/usr/bin/env bash
+# usage: ./synthesize.sh [bistream_destination]
+# If you do not specify the bitstream destination it will be saved to the
+# current directory
+
+CUR_DIR=$(pwd)
+
+QUARTUS_PROJECT_ROOT_DEFAULT="$CUR_DIR/quartus_project"
+
+# exit when error occurs
+set -e
+trap 'last_command=$current_command; current_command=$BASH_COMMAND' DEBUG
+trap 'echo "\"${last_command}\" command exited with code $?."' EXIT
+
+quartus_project_root="${QUARTUS_PROJECT_ROOT_DEFAULT}"
+
+# run synthesis
+cd $quartus_project_root/hardware_test_design
+quartus_syn --read_settings_files=on --write_settings_files=off alt_ehipc2_hw -c alt_ehipc2_hw
+quartus_fit --read_settings_files=on --write_settings_files=off alt_ehipc2_hw -c alt_ehipc2_hw
+quartus_sta alt_ehipc2_hw -c alt_ehipc2_hw --mode=finalize
+quartus_asm --read_settings_files=on --write_settings_files=off alt_ehipc2_hw -c alt_ehipc2_hw
+#cd $CUR_DIR
+#cp "$quartus_project_root/hardware_test_design/output_files/alt_ehipc2_hw.sof" \
+#    "$BITSTREAM_DESTINATION"