[Intel/Hybrid] Allows to alter Secondary Maximum Turbo Ratio Limit

cyring · Mar 30, 2022 · 7a9a994 · 7a9a994
1 parent 7b9245e
commit 7a9a994
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Showing 6 changed files with 69 additions and 6 deletions.
diff --git a/corefreq-cli-rsc-en.h b/corefreq-cli-rsc-en.h
@@ -2080,6 +2080,7 @@
 #define RSC_XAPIC_CODE			"  xAPIC"
 #define RSC_X2APIC_CODE 		" x2APIC"
 #define RSC_FIRMWARE_CODE		"Firmware"
+#define RSC_HYBRID_CODE 		"Hybrid"
 
 #define RSC_TOPOLOGY_HDR_PKG_CODE	"CPU Pkg  Apic"
 #define RSC_TOPOLOGY_HDR_SMT_CODE	"  Core/Thread"

diff --git a/corefreq-cli-rsc.c b/corefreq-cli-rsc.c
@@ -533,6 +533,7 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_ARCHITECTURE),
 	LDT(RSC_VENDOR_ID),
 	LDQ(RSC_FIRMWARE),
+	LDQ(RSC_HYBRID),
 	LDT(RSC_MICROCODE),
 	LDT(RSC_SIGNATURE),
 	LDT(RSC_STEPPING),

diff --git a/corefreq-cli-rsc.h b/corefreq-cli-rsc.h
@@ -337,6 +337,7 @@ enum {
 	RSC_ARCHITECTURE,
 	RSC_VENDOR_ID,
 	RSC_FIRMWARE,
+	RSC_HYBRID,
 	RSC_MICROCODE,
 	RSC_SIGNATURE,
 	RSC_STEPPING,

diff --git a/corefreq-cli.c b/corefreq-cli.c
@@ -936,8 +936,24 @@ void RefreshTopFreq(TGrid *grid, DATA_TYPE data)
 	struct FLIP_FLOP *CFlop = &RO(Shm)->Cpu[top].FlipFlop[
 					!RO(Shm)->Cpu[top].Toggle
 				];
-	RefreshItemFreq(grid, ratio,
-			ABS_FREQ_MHz(double, ratio, CFlop->Clock));
+	RefreshItemFreq(grid, ratio, ABS_FREQ_MHz(double, ratio, CFlop->Clock));
+}
+
+void RefreshHybridFreq(TGrid *grid, DATA_TYPE data)
+{
+	enum RATIO_BOOST boost = data.uint[0];
+	unsigned int ratio = RO(Shm)->Cpu[
+					RO(Shm)->Proc.Service.Hybrid
+				].Boost[boost];
+
+	struct FLIP_FLOP *CFlop = &RO(Shm)->Cpu[
+					RO(Shm)->Proc.Service.Hybrid
+				].FlipFlop[
+					!RO(Shm)->Cpu[
+						RO(Shm)->Proc.Service.Hybrid
+					].Toggle
+				];
+	RefreshItemFreq(grid, ratio, ABS_FREQ_MHz(double, ratio, CFlop->Clock));
 }
 
 void RefreshConfigTDP(TGrid *grid, DATA_TYPE data)
@@ -1183,7 +1199,7 @@ REASON_CODE SysInfoProc(Window *win, CUINT width, CELL_FUNC OutFunc)
     }
 	PUT(	SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.Turbo_Unlock],
 		width, 2, "%s%.*s[%7.*s]", RSC(BOOST).CODE(),
-		width - 23, hSpace, 6,
+		width - 12 - RSZ(BOOST), hSpace, 6,
 		RO(Shm)->Proc.Features.Turbo_Unlock ?
 			RSC(UNLOCK).CODE() : RSC(LOCK).CODE() );
 
@@ -1248,6 +1264,37 @@ REASON_CODE SysInfoProc(Window *win, CUINT width, CELL_FUNC OutFunc)
 				width, OutFunc, attrib[3] ),
 		RefreshTopFreq, boost );
       }
+    if (RO(Shm)->Proc.Features.ExtFeature.EDX.Hybrid == 1)
+    {
+	PUT(	SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.Turbo_Unlock],
+		width, 2, "%s%.*s[%7.*s]", RSC(HYBRID).CODE(),
+		width - 12 - RSZ(HYBRID), hSpace, 6,
+		RO(Shm)->Proc.Features.Turbo_Unlock ?
+			RSC(UNLOCK).CODE() : RSC(LOCK).CODE() );
+
+      for(boost = BOOST(1C), activeCores = 1;
+      boost > BOOST(1C)-(enum RATIO_BOOST)RO(Shm)->Proc.Features.SpecTurboRatio;
+		boost--, activeCores++)
+      {
+	CLOCK_ARG clockMod={.NC=BOXKEY_TURBO_CLOCK_NC | activeCores,.Offset=0};
+	char pfx[10+1+1];
+	StrFormat(pfx, 10+1+1, "%2uC", activeCores);
+
+	CFlop = &RO(Shm)->Cpu[
+			RO(Shm)->Proc.Service.Hybrid
+		].FlipFlop[
+			!RO(Shm)->Cpu[RO(Shm)->Proc.Service.Hybrid].Toggle
+		];
+
+	GridCall( PrintRatioFreq(win, CFlop,
+				0, pfx, &RO(Shm)->Cpu[
+						RO(Shm)->Proc.Service.Hybrid
+					].Boost[boost],
+				1, clockMod.ullong,
+				width, OutFunc, attrib[3] ),
+		RefreshHybridFreq, boost );
+      }
+    }
 
 	PUT(	SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.Uncore_Unlock],
 		width, 2, "%s%.*s[%7.*s]", RSC(UNCORE).CODE(),

diff --git a/corefreqk.c b/corefreqk.c
@@ -2565,8 +2565,19 @@ long For_All_Turbo_Clock(CLOCK_ARG *pClockMod, void (*ConfigFunc)(void *))
 static void Intel_Turbo_Cfg8C_PerCore(void *arg)
 {
 	CLOCK_TURBO_ARG *pClockCfg8C = (CLOCK_TURBO_ARG *) arg;
+	unsigned int registerAddress = MSR_TURBO_RATIO_LIMIT;
 
-	RDMSR(pClockCfg8C->Config.Cfg0, MSR_TURBO_RATIO_LIMIT);
+	if (PUBLIC(RO(Proc))->Features.ExtFeature.EDX.Hybrid == 1)
+	{
+		CORE_RO *Core;
+		unsigned int cpu = smp_processor_id();
+		Core = (CORE_RO *) PUBLIC(RO(Core, AT(cpu)));
+
+		if (Core->T.Cluster.Hybrid.CoreType == Hybrid_Atom) {
+			registerAddress = MSR_SECONDARY_TURBO_RATIO_LIMIT;
+		}
+	}
+	RDMSR(pClockCfg8C->Config.Cfg0, registerAddress);
 
   if (pClockCfg8C->pClockMod != NULL)	/* Read-Only function called ?	*/
   {
@@ -2644,8 +2655,8 @@ static void Intel_Turbo_Cfg8C_PerCore(void *arg)
 	break;
     }
       if (WrRd8C) {
-	WRMSR(pClockCfg8C->Config.Cfg0, MSR_TURBO_RATIO_LIMIT);
-	RDMSR(pClockCfg8C->Config.Cfg0, MSR_TURBO_RATIO_LIMIT);
+	WRMSR(pClockCfg8C->Config.Cfg0, registerAddress);
+	RDMSR(pClockCfg8C->Config.Cfg0, registerAddress);
 	pClockCfg8C->rc = RC_OK_COMPUTE;
       }
     } else {

diff --git a/intelmsr.h b/intelmsr.h
@@ -76,6 +76,8 @@
 	#define MSR_TURBO_RATIO_LIMIT3		0x000001ac
 #endif
 
+#define MSR_SECONDARY_TURBO_RATIO_LIMIT 	0x00000650
+
 #ifndef MSR_TURBO_POWER_CURRENT_LIMIT
 	#define MSR_TURBO_POWER_CURRENT_LIMIT	0x000001ac
 #endif