[Intel][10 to 14th Gen] Allow toggling the L1 Scrubbing

README.md

@@ -518,6 +518,7 @@ parm:           Custom_TDC_Offset:TDC Limit Offset (amp) (short)
 parm:           Activate_TDC_Limit:Activate TDC Limiting (short)
 parm:           L1_HW_PREFETCH_Disable:Disable L1 HW Prefetcher (short)
 parm:           L1_HW_IP_PREFETCH_Disable:Disable L1 HW IP Prefetcher (short)
+parm:           L1_Scrubbing_Enable:Enable L1 Scrubbing (short)
 parm:           L2_HW_PREFETCH_Disable:Disable L2 HW Prefetcher (short)
 parm:           L2_HW_CL_PREFETCH_Disable:Disable L2 HW CL Prefetcher (short)
 parm:           SpeedStep_Enable:Enable SpeedStep (short)

corefreq-api.h

@@ -896,6 +896,7 @@ typedef struct
 	BitCC			TM_Mask 	__attribute__ ((aligned (16)));
 	BitCC			ODCM_Mask	__attribute__ ((aligned (16)));
 	BitCC			DCU_Mask	__attribute__ ((aligned (16)));
+	BitCC			Scrubbing_Mask	__attribute__ ((aligned (16)));
 	BitCC			PowerMgmt_Mask	__attribute__ ((aligned (16)));
 	BitCC			SpeedStep_Mask	__attribute__ ((aligned (16)));
 	BitCC			TurboBoost_Mask __attribute__ ((aligned (16)));
@@ -1032,6 +1033,7 @@ typedef struct
 	BitCC			ODCM		__attribute__ ((aligned (16)));
 	BitCC			L1_HW_Prefetch __attribute__ ((aligned (16)));
 	BitCC			L1_HW_IP_Prefetch __attribute__((aligned (16)));
+	BitCC	/* Intel */	L1_Scrubbing	__attribute__ ((aligned (16)));
 	BitCC			L2_HW_Prefetch __attribute__ ((aligned (16)));
 	BitCC			L2_HW_CL_Prefetch __attribute__((aligned (16)));
 	BitCC			PowerMgmt	__attribute__ ((aligned (16)));

corefreq-cli-rsc-en.h

@@ -1172,6 +1172,7 @@
 #define RSC_TECHNOLOGIES_ICU_CODE_EN	"Instruction Cache Unit"
 #define RSC_TECH_L1_HW_PREFETCH_CODE_EN "L1 Prefetcher"
 #define RSC_TECH_L1_HW_IP_PREFETCH_CODE_EN "L1 IP Prefetcher"
+#define RSC_TECH_L1_SCRUBBING_CODE_EN	"L1 Scrubbing"
 #define RSC_TECH_L2_HW_PREFETCH_CODE_EN "L2 Prefetcher"
 #define RSC_TECH_L2_HW_CL_PREFETCH_CODE_EN "L2 Line Prefetcher"
 #define RSC_TECHNOLOGIES_SMM_CODE_EN	"System Management Mode"
@@ -2111,6 +2112,7 @@
 
 #define RSC_BOX_CU_L1_TITLE_CODE	" Cache Unit L1 Prefetcher "
 #define RSC_BOX_CU_L1_IP_TITLE_CODE	" Cache Unit L1 IP Prefetcher "
+#define RSC_BOX_L1_SCRUBBING_TITLE_CODE " Cache Unit L1 Scrubbing "
 #define RSC_BOX_CU_L2_TITLE_CODE	" Cache Unit L2 Prefetcher "
 #define RSC_BOX_CU_L2_CL_TITLE_CODE	" Cache Unit L2 CL Prefetcher "
 

corefreq-cli-rsc-fr.h

@@ -646,6 +646,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
 #define RSC_TECHNOLOGIES_ICU_CODE_FR  "Unit""\xa9"" de cache d'instructions"
 #define RSC_TECH_L1_HW_PREFETCH_CODE_FR "Pr""\xa9""lecteur L1"
 #define RSC_TECH_L1_HW_IP_PREFETCH_CODE_FR "Pr""\xa9""lecteur L1 IP"
+#define RSC_TECH_L1_SCRUBBING_CODE_FR	"L1 Scrubbing"
 #define RSC_TECH_L2_HW_PREFETCH_CODE_FR  "Pr""\xa9""lecteur L2"
 #define RSC_TECH_L2_HW_CL_PREFETCH_CODE_FR  "Pr""\xa9""lecteur L2 ligne"
 #define RSC_TECHNOLOGIES_SMM_CODE_FR	"Mode de Gestion Syst""\xa8""me"

corefreq-cli-rsc.c

@@ -1025,6 +1025,7 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_TECHNOLOGIES_ICU),
 	LDT(RSC_TECH_L1_HW_PREFETCH),
 	LDT(RSC_TECH_L1_HW_IP_PREFETCH),
+	LDT(RSC_TECH_L1_SCRUBBING),
 	LDT(RSC_TECH_L2_HW_PREFETCH),
 	LDT(RSC_TECH_L2_HW_CL_PREFETCH),
 	LDT(RSC_TECHNOLOGIES_SMM),
@@ -1688,6 +1689,7 @@ RESOURCE_ST Resource[] = {
 	LDT(RSC_BOX_MODE_DESC),
 	LDQ(RSC_BOX_CU_L1_TITLE),
 	LDQ(RSC_BOX_CU_L1_IP_TITLE),
+	LDQ(RSC_BOX_L1_SCRUBBING_TITLE),
 	LDQ(RSC_BOX_CU_L2_TITLE),
 	LDQ(RSC_BOX_CU_L2_CL_TITLE),
 	LDQ(RSC_BOX_EIST_TITLE),

corefreq-cli-rsc.h

@@ -828,6 +828,7 @@ enum {
 	RSC_TECHNOLOGIES_ICU,
 	RSC_TECH_L1_HW_PREFETCH,
 	RSC_TECH_L1_HW_IP_PREFETCH,
+	RSC_TECH_L1_SCRUBBING,
 	RSC_TECH_L2_HW_PREFETCH,
 	RSC_TECH_L2_HW_CL_PREFETCH,
 	RSC_TECHNOLOGIES_SMM,
@@ -1491,6 +1492,7 @@ enum {
 	RSC_BOX_MODE_DESC,
 	RSC_BOX_CU_L1_TITLE,
 	RSC_BOX_CU_L1_IP_TITLE,
+	RSC_BOX_L1_SCRUBBING_TITLE,
 	RSC_BOX_CU_L2_TITLE,
 	RSC_BOX_CU_L2_CL_TITLE,
 	RSC_BOX_EIST_TITLE,

corefreq-cli.c

@@ -3584,6 +3584,15 @@ void L1_HW_IP_Prefetch_Update(TGrid *grid, DATA_TYPE data[])
 	TechUpdate(grid, bix, pos, 3, ENABLED(bix));
 }
 
+void L1_Scrubbing_Update(TGrid *grid, DATA_TYPE data[])
+{
+	const unsigned int bix = RO(Shm)->Proc.Technology.L1_Scrubbing == 1;
+	const signed int pos = grid->cell.length - 5;
+	UNUSED(data);
+
+	TechUpdate(grid, bix, pos, 3, ENABLED(bix));
+}
+
 void L2_HW_Prefetch_Update(TGrid *grid, DATA_TYPE data[])
 {
 	const unsigned int bix = RO(Shm)->Proc.Technology.L2_HW_Prefetch == 1;
@@ -3739,6 +3748,16 @@ REASON_CODE SysInfoTech(Window *win,
 		BOXKEY_L1_HW_IP_PREFETCH,
 		L1_HW_IP_Prefetch_Update
 	},
+	{
+		(unsigned int[]) { CRC_INTEL, 0 },
+		RO(Shm)->Proc.Technology.L1_Scrubbing,
+		3, "%s%.*sL1 Scrubbing   <%3s>",
+		RSC(TECH_L1_SCRUBBING).CODE(), NULL,
+		width - (OutFunc ? 24 : 26) - RSZ(TECH_L1_SCRUBBING),
+		NULL,
+		BOXKEY_L1_SCRUBBING,
+		L1_Scrubbing_Update
+	},
 	{
 		(unsigned int[]) { CRC_INTEL, CRC_AMD, CRC_HYGON, 0 },
 		RO(Shm)->Proc.Technology.L2_HW_Prefetch,
@@ -13315,6 +13334,54 @@ int Shortcut(SCANKEY *scan)
 	}
     break;
 
+    case BOXKEY_L1_SCRUBBING:
+    {
+	Window *win = SearchWinListById(scan->key, &winList);
+      if (win == NULL)
+      {
+	const Coordinate origin = {
+		.col = (Draw.Size.width - RSZ(BOX_BLANK_DESC)) / 2,
+		.row = TOP_HEADER_ROW + 4
+	}, select = {
+		.col = 0,
+		.row = RO(Shm)->Proc.Technology.L1_Scrubbing ? 2 : 1
+	};
+	AppendWindow(
+		CreateBox(scan->key, origin, select,
+				(char*) RSC(BOX_L1_SCRUBBING_TITLE).CODE(),
+			RSC(BOX_BLANK_DESC).CODE(), blankAttr,	SCANKEY_NULL,
+			stateStr[1][RO(Shm)->Proc.Technology.L1_Scrubbing],
+			stateAttr[RO(Shm)->Proc.Technology.L1_Scrubbing],
+						BOXKEY_L1_SCRUBBING_ON,
+			stateStr[0][!RO(Shm)->Proc.Technology.L1_Scrubbing],
+			stateAttr[!RO(Shm)->Proc.Technology.L1_Scrubbing],
+						BOXKEY_L1_SCRUBBING_OFF,
+			RSC(BOX_BLANK_DESC).CODE(), blankAttr,	SCANKEY_NULL),
+		&winList);
+      } else {
+	SetHead(&winList, win);
+      }
+    }
+    break;
+
+    case BOXKEY_L1_SCRUBBING_OFF:
+	if (!RING_FULL(RW(Shm)->Ring[0])) {
+		RING_WRITE(	RW(Shm)->Ring[0],
+				COREFREQ_IOCTL_TECHNOLOGY,
+				COREFREQ_TOGGLE_OFF,
+				TECHNOLOGY_L1_SCRUBBING );
+	}
+    break;
+
+    case BOXKEY_L1_SCRUBBING_ON:
+	if (!RING_FULL(RW(Shm)->Ring[0])) {
+		RING_WRITE(	RW(Shm)->Ring[0],
+				COREFREQ_IOCTL_TECHNOLOGY,
+				COREFREQ_TOGGLE_ON,
+				TECHNOLOGY_L1_SCRUBBING );
+	}
+    break;
+
     case BOXKEY_L2_HW_PREFETCH:
     {
 	Window *win = SearchWinListById(scan->key, &winList);

corefreq-cli.h

@@ -257,6 +257,9 @@ enum KEY_ENUM {
   BOXKEY_L1_HW_IP_PREFETCH	= 0x3000000000004210LLU,
   BOXKEY_L1_HW_IP_PREFETCH_OFF	= 0x3000000000004211LLU,
   BOXKEY_L1_HW_IP_PREFETCH_ON	= 0x3000000000004212LLU,
+  BOXKEY_L1_SCRUBBING		= 0x3000000000004214LLU,
+  BOXKEY_L1_SCRUBBING_OFF	= 0x3000000000004215LLU,
+  BOXKEY_L1_SCRUBBING_ON	= 0x3000000000004216LLU,
   BOXKEY_L2_HW_PREFETCH 	= 0x3000000000004220LLU,
   BOXKEY_L2_HW_PREFETCH_OFF	= 0x3000000000004221LLU,
   BOXKEY_L2_HW_PREFETCH_ON	= 0x3000000000004222LLU,
@@ -641,6 +644,9 @@ int CheckDuplicateKey(void)			\
 	case BOXKEY_L1_HW_IP_PREFETCH:		\
 	case BOXKEY_L1_HW_IP_PREFETCH_OFF:	\
 	case BOXKEY_L1_HW_IP_PREFETCH_ON:	\
+	case BOXKEY_L1_SCRUBBING:		\
+	case BOXKEY_L1_SCRUBBING_OFF:		\
+	case BOXKEY_L1_SCRUBBING_ON:		\
 	case BOXKEY_L2_HW_PREFETCH:		\
 	case BOXKEY_L2_HW_PREFETCH_OFF: 	\
 	case BOXKEY_L2_HW_PREFETCH_ON:		\

corefreq.h

@@ -349,7 +349,8 @@ typedef struct
 				WDT		: 29-28,
 				TM1		: 31-29,
 				TM2		: 33-31,
-				_pad64		: 64-33;
+				L1_Scrubbing	: 34-33,
+				_pad64		: 64-34;
 	} Technology;
 
 	struct {

corefreqd.c

@@ -1614,6 +1614,10 @@ void Technology_Update( RO(SHM_STRUCT) *RO(Shm),
 						RW(Proc)->L1_HW_IP_Prefetch,
 						RO(Proc)->DCU_Mask);
 
+	RO(Shm)->Proc.Technology.L1_Scrubbing = BITWISEAND_CC(LOCKLESS,
+						RW(Proc)->L1_Scrubbing,
+						RO(Proc)->Scrubbing_Mask) != 0;
+
 	RO(Shm)->Proc.Technology.L2_HW_Prefetch = BITCMP_CC(LOCKLESS,
 						RW(Proc)->L2_HW_Prefetch,
 						RO(Proc)->DCU_Mask);

corefreqk.c

@@ -197,6 +197,10 @@ static signed short L1_HW_IP_PREFETCH_Disable = -1;
 module_param(L1_HW_IP_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
 MODULE_PARM_DESC(L1_HW_IP_PREFETCH_Disable, "Disable L1 HW IP Prefetcher");
 
+static signed short L1_Scrubbing_Enable = -1;
+module_param(L1_Scrubbing_Enable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
+MODULE_PARM_DESC(L1_Scrubbing_Enable, "Enable L1 Scrubbing");
+
 static signed short L2_HW_PREFETCH_Disable = -1;
 module_param(L2_HW_PREFETCH_Disable, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
 MODULE_PARM_DESC(L2_HW_PREFETCH_Disable, "Disable L2 HW Prefetcher");
@@ -8851,6 +8855,45 @@ void Intel_DCU_Technology(CORE_RO *Core)			/*Per Core */
   }
 }
 
+
+void Intel_Cache_Scrubbing(CORE_RO *Core)		/* Per P-Core	*/
+{ /* 06_7D, 06_7E, 06_8C, 06_8D, 06_97, 06_9A, 06_B7, 06_BA, 06_BF, MTL */
+  if ((Core->T.ThreadID == 0) || (Core->T.ThreadID == -1))
+  {
+    switch (Core->T.Cluster.Hybrid.CoreType) {
+    case Hybrid_Atom:
+	/*	No MSR_CORE_UARCH_CTL(0x541) register with E-Core	*/
+	break;
+    case Hybrid_Core:
+      {
+	CORE_UARCH_CTL Core_Uarch_Ctl = {.value = 0};
+	RDMSR(Core_Uarch_Ctl, MSR_CORE_UARCH_CTL);
+
+	switch (L1_Scrubbing_Enable) {
+	case COREFREQ_TOGGLE_OFF:
+	case COREFREQ_TOGGLE_ON:
+		Core_Uarch_Ctl.L1_Scrubbing_En = L1_Scrubbing_Enable;
+		WRMSR(Core_Uarch_Ctl, MSR_CORE_UARCH_CTL);
+		RDMSR(Core_Uarch_Ctl, MSR_CORE_UARCH_CTL);
+		break;
+	}
+	if (Core_Uarch_Ctl.L1_Scrubbing_En == 1) {
+		BITSET_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Scrubbing, Core->Bind);
+	} else {
+		BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Scrubbing, Core->Bind);
+	}
+	BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->Scrubbing_Mask, Core->Bind);
+      }
+	break;
+    case Hybrid_RSVD1:
+    case Hybrid_RSVD2:
+    default:
+	/*	Unspecified MSR_CORE_UARCH_CTL(0x541) register with IDs */
+	break;
+    }
+  }
+}
+
 void SpeedStep_Technology(CORE_RO *Core)			/*Per Package*/
 {
   if (Core->Bind == PUBLIC(RO(Proc))->Service.Core) {
@@ -11852,6 +11895,7 @@ void PerCore_Reset(CORE_RO *Core)
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->ODCM	, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_HW_Prefetch	, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_HW_IP_Prefetch , Core->Bind);
+	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L1_Scrubbing	, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_HW_Prefetch	, Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->L2_HW_CL_Prefetch , Core->Bind);
 	BITCLR_CC(LOCKLESS, PUBLIC(RW(Proc))->PowerMgmt , Core->Bind);
@@ -12891,6 +12935,24 @@ static void PerCore_Kaby_Lake_Query(void *arg)
 	}
 }
 
+static void PerCore_Icelake_Query(void *arg)
+{
+	CORE_RO *Core = (CORE_RO *) arg;
+
+	PerCore_Skylake_Query(arg);
+
+	Intel_Cache_Scrubbing(Core);
+}
+
+static void PerCore_Tigerlake_Query(void *arg)
+{
+	CORE_RO *Core = (CORE_RO *) arg;
+
+	PerCore_Kaby_Lake_Query(arg);
+
+	Intel_Cache_Scrubbing(Core);
+}
+
 static void PerCore_AMD_Family_0Fh_Query(void *arg)
 {
 	CORE_RO *Core = (CORE_RO *) arg;
@@ -21525,6 +21587,19 @@ static long CoreFreqK_ioctl(	struct file *filp,
 		}
 		break;
 
+	case TECHNOLOGY_L1_SCRUBBING:
+		switch (prm.dl.lo) {
+		case COREFREQ_TOGGLE_OFF:
+		case COREFREQ_TOGGLE_ON:
+			Controller_Stop(1);
+			L1_Scrubbing_Enable = prm.dl.lo;
+			Controller_Start(1);
+			L1_Scrubbing_Enable =  -1;
+			rc = RC_SUCCESS;
+			break;
+		}
+		break;
+
 	case TECHNOLOGY_L2_HW_PREFETCH:
 		switch (prm.dl.lo) {
 		case COREFREQ_TOGGLE_OFF: