x86_64 Overclocking #67

cyring · 2018-07-26T15:18:28Z

In the specifications of MSR_PLATFORM_INFO for architecture signature 06_3AH the bit 28 has the following definition:

Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limit for Turbo mode is enabled. When set to 0,
indicates Programmable Ratio Limit for Turbo mode is disabled.

Edit: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz has the Ratios reported correctly locked.

Processor                             [ Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz]
|- Architecture                                                      [IvyBridge]
|- Vendor ID                                                      [GenuineIntel]
|- Signature                                                            [ 06_3A]
|- Stepping                                                             [     9]
|- Microcode                                                            [     0]
|- Online CPU                                                           [  8/8 ]
|- Base Clock                                                           [ 98.97]
|- Overclocking                                                         [  LOCK]
|- Frequency            (Mhz)                      Ratio                        
                 Min   1583.59                    [  16 ]                       
                 Max   3365.12                    [  34 ]                       
|- Factory                                                                      
                       3400                       [  34 ]               [100.00]
|- Turbo Boost                                                                  
                  1C   3860.00                    [  39 ]                       
                  2C   3860.00                    [  39 ]                       
                  3C   3761.02                    [  38 ]                       
                  4C   3662.05                    [  37 ]                       
|- Uncore                                                                       
                 Min   1583.59                    [  16 ]                       
                 Max   3365.12                    [  34 ]                       
                                                                                
ISA Extensions:                                                                 
|- 3DNow!/Ext [N,N]        AES [Y]   AVX/AVX2 [Y/N]   BMI1/BMI2 [N/N] 
|- CLFSH        [Y]       CMOV [Y]      CMPXCH8 [Y]      CMPXCH16 [Y] 
|- F16C         [Y]        FPU [Y]         FXSR [Y]     LAHF/SAHF [Y] 
|- MMX/Ext    [Y/N]    MONITOR [Y]        MOVBE [N]      PCLMULDQ [Y] 
|- POPCNT       [Y]     RDRAND [Y]       RDTSCP [Y]           SEP [Y] 
|- SGX          [N]        SSE [Y]         SSE2 [Y]          SSE3 [Y] 
|- SSSE3        [Y] SSE4.1/4A [Y/N]      SSE4.2 [Y]       SYSCALL [Y] 
                                                                                
Features:                                                                       
|- 1 GB Pages Support                                      1GB-PAGES   [Missing]
|- 100 MHz multiplier Control                            100MHzSteps   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Present]
|- Advanced Programmable Interrupt Controller                   APIC   [Present]
|- Core Multi-Processing                                  CMP Legacy   [Missing]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Present]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Present]
|- CPL Qualified Debug Store                                  DS-CPL   [Present]
|- 64-Bit Debug Store                                         DTES64   [Present]
|- Fast-String Operation                                Fast-Strings   [Present]
|- Fused Multiply Add                                       FMA|FMA4   [Missing]
|- Hardware Lock Elision                                         HLE   [Missing]
|- Long Mode 64 bits                                         IA64|LM   [Present]
|- LightWeight Profiling                                         LWP   [Missing]
|- Machine-Check Architecture                                    MCA   [Present]
|- Model Specific Registers                                      MSR   [Present]
|- Memory Type Range Registers                                  MTRR   [Present]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Present]
|- Physical Address Extension                                    PAE   [Present]
|- Page Attribute Table                                          PAT   [Present]
|- Pending Break Enable                                          PBE   [Present]
|- Process Context Identifiers                                  PCID   [Present]
|- Perfmon and Debug Capability                                 PDCM   [Present]
|- Page Global Enable                                            PGE   [Present]
|- Page Size Extension                                           PSE   [Present]
|- 36-bit Page Size Extension                                  PSE36   [Present]
|- Processor Serial Number                                       PSN   [Missing]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Present]
|- Self-Snoop                                                     SS   [Present]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Present]
|- Virtual Mode Extension                                        VME   [Present]
|- Virtual Machine Extensions                                    VMX   [Present]
|- Extended xAPIC Support                                     x2APIC   [ x2APIC]
|- Execution Disable Bit Support                              XD-Bit   [Present]
|- XSAVE/XSTOR States                                          XSAVE   [Present]
|- xTPR Update Control                                          xTPR   [Present]
                                                                                
Technologies:                                                                   
|- System Management Mode                                   SMM-Dual       [ ON]
|- Hyper-Threading                                               HTT       [ ON]
|- SpeedStep                                                    EIST       < ON>
|- Dynamic Acceleration                                          IDA       [ ON]
|- Turbo Boost                                                 TURBO       < ON>
|- Virtualization                                                VMX       [ ON]
   |- I/O MMU                                                   VT-d       [OFF]
   |- Hypervisor                                                           [OFF]
                                                                                
Performance Monitoring:                                                         
|- Version                                                        PM       [  3]
|- Counters:          General                   Fixed                           
|                     4 x 48 bits             3 x 48 bits                       
|- Enhanced Halt State                                           C1E       < ON>
|- C1 Auto Demotion                                              C1A       < ON>
|- C3 Auto Demotion                                              C3A       < ON>
|- C1 UnDemotion                                                 C1U       < ON>
|- C3 UnDemotion                                                 C3U       < ON>
|- Frequency ID control                                          FID       [OFF]
|- Voltage ID control                                            VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Hardware-Controlled Performance States                        HWP       [OFF]
|- Hardware Duty Cycling                                         HDC       [OFF]
|- Package C-State                                                              
   |- Configuration Control                                   CONFIG   [   LOCK]
   |- Lowest C-State                                           LIMIT   [      6]
   |- I/O MWAIT Redirection                                  IOMWAIT   [ ENABLE]
   |- Max C-State Inclusion                                    RANGE   [      6]
|- MWAIT States:      C0      C1      C2      C3      C4                        
|                      0       2       1       1       0                        
|- Core Cycles                                                         [Present]
|- Instructions Retired                                                [Present]
|- Reference Cycles                                                    [Present]
|- Last Level Cache References                                         [Present]
|- Last Level Cache Misses                                             [Present]
|- Branch Instructions Retired                                         [Present]
|- Branch Mispredicts Retired                                          [Present]
                                                                                
Power & Thermal Monitoring:                                                     
|- Clock Modulation                                             ODCM   <Disable>
   |- DutyCycle                                                        <  6.25%>
|- Power Management                                         PWR MGMT   [   LOCK]
   |- Energy Policy                                        Bias Hint   [      0]
|- Junction Temperature                                        TjMax   [    105]
|- Digital Thermal Sensor                                        DTS   [Present]
|- Power Limit Notification                                      PLN   [Present]
|- Package Thermal Management                                    PTM   [Present]
|- Thermal Monitor 1                                         TM1|TTP   [ Enable]
|- Thermal Monitor 2                                         TM2|HTC   [Present]
|- Units                                                                        
   |- Power                                               watt   [  0.125000000]
   |- Energy                                             joule   [  0.000015259]
   |- Window                                            second   [  0.000976562]

The text was updated successfully, but these errors were encountered:

cyring · 2018-07-27T19:35:50Z

Changed the bits decoding of MSR PLATFORM INFO. Overclocking exceptions remain feasible through the Specifics list.
This issue stays opened for any user request of model addition.

cyring · 2018-07-30T09:41:36Z

Need to blacklist overclocking on the i5-7500 which reports unlocked ratios.

Processor                              [Intel(R) Core(TM) i5-7500 CPU @ 3.40GHz]
|- Architecture                                               [Kaby/Coffee Lake]
|- Vendor ID                                                      [GenuineIntel]
|- Signature                                                            [ 06_9E]
|- Stepping                                                             [     9]
|- Microcode                                                            [     0]
|- Online CPU                                                           [  4/4 ]
|- Base Clock                                                           [ 99.44]
|- Overclocking                                                         [UNLOCK]
|- Frequency            (Mhz)                      Ratio                        
                 Min    795.55                    [   8 ]                       
                 Max   3381.08                    [  34 ]                       
|- Factory                                                                      
                       3400                       [  34 ]               [100.00]
|- Turbo Boost                                                                  
                  1C   3778.85                    <  38 >                       
                  2C   3679.41                    <  37 >                       
                  3C   3679.41                    <  37 >                       
                  4C   3579.96                    <  36 >                       
|- Uncore                                                                       
                 Min    795.55                    [   8 ]                       
                 Max   3480.52                    [  35 ]                       
                                                                                
ISA Extensions:                                                                 
|- 3DNow!/Ext [N,N]        AES [Y]   AVX/AVX2 [Y/Y]   BMI1/BMI2 [Y/Y] 
|- CLFSH        [Y]       CMOV [Y]      CMPXCH8 [Y]      CMPXCH16 [Y] 
|- F16C         [Y]        FPU [Y]         FXSR [Y]     LAHF/SAHF [Y] 
|- MMX/Ext    [Y/N]    MONITOR [Y]        MOVBE [Y]      PCLMULDQ [Y] 
|- POPCNT       [Y]     RDRAND [Y]       RDTSCP [Y]           SEP [Y] 
|- SGX          [Y]        SSE [Y]         SSE2 [Y]          SSE3 [Y] 
|- SSSE3        [Y] SSE4.1/4A [Y/N]      SSE4.2 [Y]       SYSCALL [Y] 
                                                                                
Features:                                                                       
|- 1 GB Pages Support                                      1GB-PAGES   [Present]
|- 100 MHz multiplier Control                            100MHzSteps   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Present]
|- Advanced Programmable Interrupt Controller                   APIC   [Present]
|- Core Multi-Processing                                  CMP Legacy   [Missing]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Present]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Present]
|- CPL Qualified Debug Store                                  DS-CPL   [Present]
|- 64-Bit Debug Store                                         DTES64   [Present]
|- Fast-String Operation                                Fast-Strings   [Present]
|- Fused Multiply Add                                       FMA|FMA4   [Present]
|- Hardware Lock Elision                                         HLE   [Present]
|- Long Mode 64 bits                                         IA64|LM   [Present]
|- LightWeight Profiling                                         LWP   [Missing]
|- Machine-Check Architecture                                    MCA   [Present]
|- Model Specific Registers                                      MSR   [Present]
|- Memory Type Range Registers                                  MTRR   [Present]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Present]
|- Physical Address Extension                                    PAE   [Present]
|- Page Attribute Table                                          PAT   [Present]
|- Pending Break Enable                                          PBE   [Present]
|- Process Context Identifiers                                  PCID   [Present]
|- Perfmon and Debug Capability                                 PDCM   [Present]
|- Page Global Enable                                            PGE   [Present]
|- Page Size Extension                                           PSE   [Present]
|- 36-bit Page Size Extension                                  PSE36   [Present]
|- Processor Serial Number                                       PSN   [Missing]
|- Restricted Transactional Memory                               RTM   [Present]
|- Safer Mode Extensions                                         SMX   [Present]
|- Self-Snoop                                                     SS   [Present]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Present]
|- Virtual Mode Extension                                        VME   [Present]
|- Virtual Machine Extensions                                    VMX   [Present]
|- Extended xAPIC Support                                     x2APIC   [ x2APIC]
|- Execution Disable Bit Support                              XD-Bit   [Present]
|- XSAVE/XSTOR States                                          XSAVE   [Present]
|- xTPR Update Control                                          xTPR   [Present]
                                                                                
Technologies:                                                                   
|- System Management Mode                                   SMM-Dual       [ ON]
|- Hyper-Threading                                               HTT       [OFF]
|- SpeedStep                                                    EIST       < ON>
|- Dynamic Acceleration                                          IDA       [ ON]
|- Turbo Boost                                                 TURBO       < ON>
|- Virtualization                                                VMX       [ ON]
   |- I/O MMU                                                   VT-d       [OFF]
   |- Hypervisor                                                           [OFF]
                                                                                
Performance Monitoring:                                                         
|- Version                                                        PM       [  4]
|- Counters:          General                   Fixed                           
|                     8 x 48 bits             3 x 48 bits                       
|- Enhanced Halt State                                           C1E       <OFF>
|- C1 Auto Demotion                                              C1A       < ON>
|- C3 Auto Demotion                                              C3A       < ON>
|- C1 UnDemotion                                                 C1U       < ON>
|- C3 UnDemotion                                                 C3U       < ON>
|- Frequency ID control                                          FID       [OFF]
|- Voltage ID control                                            VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Hardware-Controlled Performance States                        HWP       [ ON]
|- Hardware Duty Cycling                                         HDC       [ ON]
|- Package C-State                                                              
   |- Configuration Control                                   CONFIG   [   LOCK]
   |- Lowest C-State                                           LIMIT   [      0]
   |- I/O MWAIT Redirection                                  IOMWAIT   [DISABLE]
   |- Max C-State Inclusion                                    RANGE   [      0]
|- MWAIT States:      C0      C1      C2      C3      C4                        
|                      0       2       1       2       4                        
|- Core Cycles                                                         [Present]
|- Instructions Retired                                                [Present]
|- Reference Cycles                                                    [Present]
|- Last Level Cache References                                         [Present]
|- Last Level Cache Misses                                             [Present]
|- Branch Instructions Retired                                         [Present]
|- Branch Mispredicts Retired                                          [Present]
                                                                                
Power & Thermal Monitoring:                                                     
|- Clock Modulation                                             ODCM   <Disable>
   |- DutyCycle                                                        <  6.25%>
|- Power Management                                         PWR MGMT   [   LOCK]
   |- Energy Policy                                        Bias Hint   [      0]
|- Junction Temperature                                        TjMax   [    100]
|- Digital Thermal Sensor                                        DTS   [Present]
|- Power Limit Notification                                      PLN   [Present]
|- Package Thermal Management                                    PTM   [Present]
|- Thermal Monitor 1                                         TM1|TTP   [ Enable]
|- Thermal Monitor 2                                         TM2|HTC   [Present]
|- Units                                                                        
   |- Power                                               watt   [  0.125000000]
   |- Energy                                             joule   [  0.000061035]
   |- Window                                            second   [  0.000976562]

Fix to apply in corefreqk.h

static PROCESSOR_SPECIFIC Kabylake_Specific[] = {
	{
	.brandSubStr = "Intel(R) Core(TM) i5-7500 CPU",
	.ratioUnlocked = 0
	},
	{NULL, 0}
};

/* 42*/	{
	.Signature = _Kabylake,
	.Query = Query_Broadwell,
	.Update = PerCore_Skylake_Query,
	.Start = Start_Skylake,
	.Stop = Stop_Skylake,
	.Exit = NULL,
	.Timer = InitTimer_Skylake,
	.BaseClock = BaseClock_Skylake,
	.OverClock = Intel_Turbo_Config8C,
	.Architecture = "Kaby/Coffee Lake",
	.thermalFormula = THERMAL_FORMULA_INTEL,
	.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
	.powerFormula   = POWER_FORMULA_INTEL,
	.PCI_ids = PCI_Kabylake_ids,
	.Uncore = {
		.Start = Start_Uncore_Skylake,
		.Stop = Stop_Uncore_Skylake
		},
	.Specific = Kabylake_Specific
	},

cyring · 2018-07-31T14:25:08Z

Fix the vertical alignment of ratio at offset 0

CoreFreq/corefreq-cli.c

Line 3499 in 93ee0f1

wOC->matrix.scroll.vert = (hthMax - hthWin) >> 1;

		wOC->matrix.scroll.vert = hthMax >> 1;

cyring · 2018-08-01T13:16:40Z

Max and Min Uncore overclocking is successfully tested

Fix for the selection window in corefreq-cli.c

    Window *CreateUC(unsigned long long id)
    {
	ATTRIBUTE attribute[2][28] = {
		{
		LWK,HWK,HWK,HWK,HWK,LWK,HWK,HWK,LWK,HDK,HDK,HDK,LWK,LWK,
		LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK
		},
		{
		LWK,HRK,HRK,HRK,HRK,LRK,HRK,HRK,LWK,HDK,HDK,HDK,LWK,LWK,
		LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK
		}
	};
	ASCII item[32];
	CLOCK_ARG overclock  = {.sllong = id};
	unsigned int ratio = overclock.Ratio & OVERCLOCK_RATIO_MASK, multiplier;
	signed int offset,
	lowestOperatingShift = abs(Shm->Uncore.Boost[UNCORE_BOOST(SIZE) - ratio]
				 - Shm->Proc.Boost[BOOST(MIN)]),
	highestOperatingShift	= Shm->Proc.Features.Factory.Ratio
				+(Shm->Proc.Features.Factory.Ratio >> 3)
				- Shm->Uncore.Boost[UNCORE_BOOST(SIZE) - ratio];
	const CUINT	hthMin = 16;
		CUINT	hthMax = 1 + lowestOperatingShift+highestOperatingShift,
			hthWin = CUMIN(hthMin, hthMax);

	Window *wUC = CreateWindow(wLayer, id, 1, hthWin, 40,
				(TOP_HEADER_ROW + hthWin+2 < drawSize.height) ?
					TOP_HEADER_ROW + 2 : 1);
      if (wUC != NULL) {
	for (offset = -lowestOperatingShift;
		offset <= highestOperatingShift;
			offset++)
		{
		overclock.Ratio = ratio | BOXKEY_UNCORE_CLOCK;
		overclock.Offset = offset;
		multiplier = Shm->Uncore.Boost[UNCORE_BOOST(SIZE) - ratio];
		multiplier += offset;

		sprintf((char*) item, " %7.2f MHz   [%4d ]  %+3d ",
			(double)(multiplier
				* Shm->Cpu[Shm->Proc.Service.Core].Clock.Hz)
				/ 1000000.0,
			multiplier, offset);

		StoreTCell(wUC, overclock.sllong, item,
			attribute[multiplier > Shm->Proc.Features.Factory.Ratio?
					1 : 0]);
		}
	sprintf((char*) item, " %s Clock Uncore ", ratio == 1 ? "Max" : "Min");
	StoreWindow(wUC, .title, (char*) item);

	if (lowestOperatingShift >= hthWin) {
		wUC->matrix.scroll.vert = hthMax
					- hthWin * (1 + (highestOperatingShift
							/ hthWin));
		wUC->matrix.select.row  = lowestOperatingShift
					- wUC->matrix.scroll.vert;
	} else {
		wUC->matrix.select.row  = lowestOperatingShift;
	}
	StoreWindow(wUC,	.key.Enter,	MotionEnter_Cell);
	StoreWindow(wUC,	.key.Down,	MotionDown_Win);
	StoreWindow(wUC,	.key.Up,	MotionUp_Win);
	StoreWindow(wUC,	.key.PgUp,	MotionPgUp_Win);
	StoreWindow(wUC,	.key.PgDw,	MotionPgDw_Win);
	StoreWindow(wUC,	.key.Home,	MotionTop_Win);
	StoreWindow(wUC,	.key.End,	MotionBottom_Win);

	StoreWindow(wUC,	.key.WinLeft,	MotionOriginLeft_Win);
	StoreWindow(wUC,	.key.WinRight,	MotionOriginRight_Win);
	StoreWindow(wUC,	.key.WinDown,	MotionOriginDown_Win);
	StoreWindow(wUC,	.key.WinUp,	MotionOriginUp_Win);
      }
	return(wUC);
    }

cyring · 2018-08-03T11:43:03Z

i5-7300U [KBL/UY]

CoreFreq/corefreq-cli.c

Line 3452 in 6712f73

Window *CreateOC(unsigned long long id)

    Window *CreateOC(unsigned long long id)
    {
	ATTRIBUTE attribute[3][28] = {
		{
		LWK,HWK,HWK,HWK,HWK,LWK,HWK,HWK,LWK,HDK,HDK,HDK,LWK,LWK,
		LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK
		},
		{
		LWK,HBK,HBK,HBK,HBK,LBK,HBK,HBK,LWK,HDK,HDK,HDK,LWK,LWK,
		LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK
		},
		{
		LWK,HRK,HRK,HRK,HRK,LRK,HRK,HRK,LWK,HDK,HDK,HDK,LWK,LWK,
		LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK
		}
	};
	ASCII item[32];
	CLOCK_ARG overclock  = {.sllong = id};
	unsigned int ratio = overclock.Ratio & OVERCLOCK_RATIO_MASK, multiplier;
	signed int offset,
		lowestOperatingShift= abs(Shm->Proc.Boost[BOOST(SIZE) - ratio]
					- Shm->Proc.Boost[BOOST(MIN)]),
		medianColdZone =( Shm->Proc.Boost[BOOST(MIN)]
				+ Shm->Proc.Features.Factory.Ratio ) >> 1,
		startingHotZone = Shm->Proc.Features.Factory.Ratio
				+(Shm->Proc.Features.Factory.Ratio * 2 / 5),
		highestOperatingShift = (unsigned int) (5100000000.0
				/ Shm->Cpu[Shm->Proc.Service.Core].Clock.Hz)
				- Shm->Proc.Boost[BOOST(SIZE) - ratio];
	const CUINT	hthMin = 16;
		CUINT	hthMax = 1+lowestOperatingShift + highestOperatingShift,
			hthWin = CUMIN(hthMin, hthMax);

	Window *wOC = CreateWindow(wLayer, id, 1, hthWin, 34,
				(TOP_HEADER_ROW + hthWin+2 < drawSize.height) ?
					TOP_HEADER_ROW + 2 : 1);
      if (wOC != NULL) {
	for (offset = -lowestOperatingShift;
		offset <= highestOperatingShift;
			offset++)
		{
		overclock.Ratio = ratio | BOXKEY_OVERCLOCK;
		overclock.Offset = offset;
		multiplier = Shm->Proc.Boost[BOOST(SIZE) - ratio] + offset;

		sprintf((char*) item, " %7.2f MHz   [%4d ]  %+3d ",
			(double)(multiplier
				* Shm->Cpu[Shm->Proc.Service.Core].Clock.Hz)
				/ 1000000.0,
			multiplier, offset);

		StoreTCell(wOC, overclock.sllong, item,
			attribute[multiplier < medianColdZone ?
					1 : multiplier >= startingHotZone ?
						2 : 0]);
		}
	sprintf((char*) item, " Under/Over-Clock %1dC ", ratio);
	StoreWindow(wOC, .title, (char*) item);

	if (lowestOperatingShift >= hthWin) {
		wOC->matrix.scroll.vert = hthMax
					- hthWin * (1 + (highestOperatingShift
							/ hthWin));
		wOC->matrix.select.row  = lowestOperatingShift
					- wOC->matrix.scroll.vert;
	} else {
		wOC->matrix.select.row  = lowestOperatingShift;
	}
	StoreWindow(wOC,	.key.Enter,	MotionEnter_Cell);
	StoreWindow(wOC,	.key.Down,	MotionDown_Win);
	StoreWindow(wOC,	.key.Up,	MotionUp_Win);
	StoreWindow(wOC,	.key.PgUp,	MotionPgUp_Win);
	StoreWindow(wOC,	.key.PgDw,	MotionPgDw_Win);
	StoreWindow(wOC,	.key.Home,	MotionTop_Win);
	StoreWindow(wOC,	.key.End,	MotionBottom_Win);

	StoreWindow(wOC,	.key.WinLeft,	MotionOriginLeft_Win);
	StoreWindow(wOC,	.key.WinRight,	MotionOriginRight_Win);
	StoreWindow(wOC,	.key.WinDown,	MotionOriginDown_Win);
	StoreWindow(wOC,	.key.WinUp,	MotionOriginUp_Win);
      }
	return(wOC);
    }

    Window *CreateUC(unsigned long long id)
    {
	ATTRIBUTE attribute[2][28] = {
		{
		LWK,HWK,HWK,HWK,HWK,LWK,HWK,HWK,LWK,HDK,HDK,HDK,LWK,LWK,
		LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK
		},
		{
		LWK,HRK,HRK,HRK,HRK,LRK,HRK,HRK,LWK,HDK,HDK,HDK,LWK,LWK,
		LWK,LWK,HWK,HWK,HWK,HWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK
		}
	};
	ASCII item[32];
	CLOCK_ARG overclock  = {.sllong = id};
	unsigned int ratio = overclock.Ratio & OVERCLOCK_RATIO_MASK, multiplier;
	signed int offset,
	lowestOperatingShift = abs(Shm->Uncore.Boost[UNCORE_BOOST(SIZE) - ratio]
				 - Shm->Proc.Boost[BOOST(MIN)]),
	highestOperatingShift	= Shm->Proc.Features.Factory.Ratio
				+(Shm->Proc.Features.Factory.Ratio >> 1)
				- Shm->Uncore.Boost[UNCORE_BOOST(SIZE) - ratio],
	startingHotZone = Shm->Proc.Features.Factory.Ratio + 
			+(Shm->Proc.Features.Factory.Ratio * 2 / 5);
	const CUINT	hthMin = 16;
		CUINT	hthMax = 1+lowestOperatingShift + highestOperatingShift,
			hthWin = CUMIN(hthMin, hthMax);

	Window *wUC = CreateWindow(wLayer, id, 1, hthWin, 40,
				(TOP_HEADER_ROW + hthWin+2 < drawSize.height) ?
					TOP_HEADER_ROW + 2 : 1);
      if (wUC != NULL) {
	for (offset = -lowestOperatingShift;
		offset <= highestOperatingShift;
			offset++)
		{
		overclock.Ratio = ratio | BOXKEY_UNCORE_CLOCK;
		overclock.Offset = offset;
		multiplier = Shm->Uncore.Boost[UNCORE_BOOST(SIZE) - ratio];
		multiplier += offset;

		sprintf((char*) item, " %7.2f MHz   [%4d ]  %+3d ",
			(double)(multiplier
				* Shm->Cpu[Shm->Proc.Service.Core].Clock.Hz)
				/ 1000000.0,
			multiplier, offset);

		StoreTCell(wUC, overclock.sllong, item,
			attribute[multiplier > startingHotZone ? 1 : 0]);
		}
	sprintf((char*) item, " %s Clock Uncore ", ratio == 1 ? "Max" : "Min");
	StoreWindow(wUC, .title, (char*) item);

	if (lowestOperatingShift >= hthWin) {
		wUC->matrix.scroll.vert = hthMax
					- hthWin * (1 + (highestOperatingShift
							/ hthWin));
		wUC->matrix.select.row  = lowestOperatingShift
					- wUC->matrix.scroll.vert;
	} else {
		wUC->matrix.select.row  = lowestOperatingShift;
	}
	StoreWindow(wUC,	.key.Enter,	MotionEnter_Cell);
	StoreWindow(wUC,	.key.Down,	MotionDown_Win);
	StoreWindow(wUC,	.key.Up,	MotionUp_Win);
	StoreWindow(wUC,	.key.PgUp,	MotionPgUp_Win);
	StoreWindow(wUC,	.key.PgDw,	MotionPgDw_Win);
	StoreWindow(wUC,	.key.Home,	MotionTop_Win);
	StoreWindow(wUC,	.key.End,	MotionBottom_Win);

	StoreWindow(wUC,	.key.WinLeft,	MotionOriginLeft_Win);
	StoreWindow(wUC,	.key.WinRight,	MotionOriginRight_Win);
	StoreWindow(wUC,	.key.WinDown,	MotionOriginDown_Win);
	StoreWindow(wUC,	.key.WinUp,	MotionOriginUp_Win);
      }
	return(wUC);
    }

CoreFreq/corefreqk.c

Line 2798 in 6712f73

void Query_Broadwell(void)

void Query_Broadwell(void)
{
	Proc->Features.Uncore_Unlock = 1;
	Nehalem_Platform_Info();
	HyperThreading_Technology();
	Haswell_Uncore_Ratio(NULL);
	SandyBridge_PowerInterface();
}

CoreFreq/corefreqk.h

Line 1698 in 6712f73

/* 30*/ {

/* 30*/	{
	.Signature = _Haswell_DT,
	.Query = Query_Haswell,
	.Update = PerCore_IvyBridge_Query,
	.Start = Start_SandyBridge,
	.Stop = Stop_SandyBridge,
	.Exit = NULL,
	.Timer = InitTimer_SandyBridge,
	.BaseClock = BaseClock_Haswell,
	.OverClock = Intel_Turbo_Config8C,
	.Architecture = "Haswell/Desktop",
	.thermalFormula = THERMAL_FORMULA_INTEL,
	.voltageFormula = VOLTAGE_FORMULA_INTEL_SNB,
	.powerFormula   = POWER_FORMULA_INTEL,
	.PCI_ids = PCI_Haswell_ids,
	.Uncore = {
		.Start = Start_Uncore_SandyBridge,
		.Stop = Stop_Uncore_SandyBridge
		},
	.Specific = Void_Specific
	},

CoreFreq/corefreqk.h

Line 499 in 6712f73

extern void Query_Haswell_EP(void) ;

extern void Query_Haswell(void) ;

CoreFreq/corefreqk.c

Line 2790 in 6712f73

void Query_Haswell_EP(void)

void Query_Haswell(void)
{
	Proc->Features.Uncore_Unlock = 1;
	Nehalem_Platform_Info();
	HyperThreading_Technology();
	SandyBridge_Uncore_Ratio();
	Intel_Turbo_TDP_Config();
	SandyBridge_PowerInterface();
}

cyring · 2018-08-15T13:58:41Z

Code backported

cyring · 2019-05-08T09:15:51Z

Reopening case based on this last experimentation.

The BIOS has been set with the following parameters :

Turbo is disable
CPU ratio is set to 28
C-States, EIST, C1E, C1A, C3A enable
Base clock is set to its factory value 133.333 MHz

The Kernel runs in POLL mode with this command line:

idle=poll processor.max_cstate=1 intel_idle.max_cstate=0 cpufreq.off=1 intel_pstate=disable nmi_watchdog=0 modprobe.blacklist=pcspkr,iTCO_wdt,intel_cstate,intel_uncore,intel_powerclamp,i7core_edac,aesni_intel,ghash_clmulni_intel,crc32c_intel,crypto-crc32c-intel,i5500_temp,vboxnetflt,vboxnetadp,vboxpci,vboxdrv,kvm_intel,kvm,coretemp cpu0_hotplug audit=0

Results with BIOS CPU coefficient locked
BIOS CPU coefficient set to Auto

System is reboot with the CPU ratio set to Auto in BIOS
The Kernel is boot with idle=nomwait
Nominal values
Target = Target + 1
Turbo 6C = Turbo 6C + 1
Again, Turbo 6C = Turbo 6C + 1

Conclusion (partial)
The Max Frequency is a function of :

Turbo register with the highest Simultaneous Core Count ratio in action
Target OSPM ratio set to 1 + max non boosted ratio

C-States governed by ACPI

In BIOS: coefficient set to Auto and Turbo is enable
The Kernel command line is changed to allow C-States governed by ACPI only; without the intel_cstate idle driver.

idle=mwait processor.max_cstate=6 intel_idle.max_cstate=0 cpufreq.off=1 intel_pstate=disable elevator=noop nmi_watchdog=0 modprobe.blacklist=pcspkr,iTCO_wdt,intel_cstate,intel_uncore,intel_powerclamp,i7core_edac,aesni_intel,ghash_clmulni_intel,crc32c_intel,crypto-crc32c-intel,i5500_temp,vboxnetflt,vboxnetadp,vboxpci,vboxdrv,kvm_intel,kvm,coretemp cpu0_hotplug audit=0

Initial state
Turbo enable by CoreFreq

Conclusion (partial)
The Max Frequency is now a function of :

Turbo register with One Core Count ratio in action
Target OSPM ratio set to 1 + max non boosted ratio

cyring · 2019-05-08T09:46:04Z

Kernel x86_64 functions

Start

start_kernel()
___ -> check_bugs()
_________ -> identify_boot_cpu()
_______________ -> identify_cpu()
_____________________ -> select_idle_routine()

`select_idle_routine()`

default_idle() -> asm volatile("sti; hlt": : :"memory")
mwait_idle()
___ -> __monitor((void *)&current_thread_info()->flags, 0, 0)
_________ -> asm volatile(".byte 0x0f, 0x01, 0xc8;" :: "a" (eax), "c" (ecx), "d"(edx))
___ -> __sti_mwait(unsigned long eax, unsigned long ecx)
_________ -> asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" :: "a" (eax), "c" (ecx))

SMP

mwait_play_dead()
___ -> __monitor(mwait_ptr, 0, 0)
_________ -> asm volatile(".byte 0x0f, 0x01, 0xc8;" :: "a" (eax), "c" (ecx), "d"(edx))
___ -> __mwait(eax, 0)
_________ -> asm volatile(".byte 0x0f, 0x01, 0xc9;" :: "a" (eax), "c" (ecx))

The idle loop implementation

do_idle
___ -> cpu_idle_poll()
_________ -> cpu_relax()
_______________ -> asm volatile("rep; nop" ::: "memory")
OR
___ -> cpuidle_idle_call()
_________ -> default_idle_call()
_______________ -> arch_cpu_idle()
_____________________ -> x86_idle() as a function of select_idle_routine()
___________________________ -> default_idle()
___________________________ OR
___________________________ -> mwait_idle()
_________ OR
_________ -> call_cpuidle()
_______________ -> cpuidle_enter()
_____________________ -> cpuidle_enter_state()
___________________________ -> target_state->enter() is one driver idle function vector

Registers & Instructions

across all architectures
IA32_MONITOR_FILTER_SIZE (0x6)

cyring · 2019-09-02T13:59:20Z

Idle & Frequency sub-drivers implemented.

cyring added the bug label Jul 26, 2018

cyring self-assigned this Jul 26, 2018

cyring added bugfix and removed bug labels Jul 27, 2018

cyring added the enhancement label Jul 27, 2018

cyring changed the title ~~Overclocking blacklist~~ Overclocking black-or-whitelist Jul 27, 2018

cyring mentioned this issue Jul 28, 2018

Nehalem: Programmable Ratio Limit for Turbo Mode #62

Closed

cyring removed the bugfix label Jul 30, 2018

cyring added a commit that referenced this issue Jul 31, 2018

Misc specifics Core OC (issue #67) / Uncore OC (testing only)

21f6dfa

cyring added a commit that referenced this issue Aug 2, 2018

Improved the Uncore clock selector (issue #67)

6712f73

cyring added a commit that referenced this issue Aug 3, 2018

Code backport for RAPL issue #57 and Uncore overclocking issue #67

2a4af30

cyring closed this as completed Aug 15, 2018

cyring reopened this May 8, 2019

cyring changed the title ~~Overclocking black-or-whitelist~~ Intel Overclocking May 8, 2019

cyring changed the title ~~Intel Overclocking~~ x86_64 Overclocking May 8, 2019

cyring closed this as completed Sep 2, 2019

This was referenced Dec 28, 2022

Ryzen 9 7950X #378

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x86_64 Overclocking #67

x86_64 Overclocking #67

cyring commented Jul 26, 2018 •

edited

cyring commented Jul 27, 2018

cyring commented Jul 30, 2018 •

edited

cyring commented Jul 31, 2018 •

edited

cyring commented Aug 1, 2018 •

edited

cyring commented Aug 3, 2018 •

edited

cyring commented Aug 15, 2018

cyring commented May 8, 2019 •

edited

cyring commented May 8, 2019 •

edited

cyring commented Sep 2, 2019

x86_64 Overclocking #67

x86_64 Overclocking #67

Comments

cyring commented Jul 26, 2018 • edited

cyring commented Jul 27, 2018

cyring commented Jul 30, 2018 • edited

cyring commented Jul 31, 2018 • edited

cyring commented Aug 1, 2018 • edited

cyring commented Aug 3, 2018 • edited

cyring commented Aug 15, 2018

cyring commented May 8, 2019 • edited

cyring commented May 8, 2019 • edited

Kernel x86_64 functions

Start

select_idle_routine()

SMP

The idle loop implementation

Registers & Instructions

cyring commented Sep 2, 2019

cyring commented Jul 26, 2018 •

edited

cyring commented Jul 30, 2018 •

edited

cyring commented Jul 31, 2018 •

edited

cyring commented Aug 1, 2018 •

edited

cyring commented Aug 3, 2018 •

edited

cyring commented May 8, 2019 •

edited

cyring commented May 8, 2019 •

edited

`select_idle_routine()`