Repository for Computer Systems Architecture project.
AY 2019/2020
Group project consisting in accomplishing different exercises about VHDL components. It starts from building basic components such as mux and shift registers to complex systems in both microprogrammed and cabled logic.
Most of the components were also implementd on FPGA boards such as Digilent Basys and Digilent Nexys 2.
Xilinx ISE Desgin suite was used as IDE for programming both components and FPGA boards.
Detailed description of assigned exercises can be found here.
Complete documentation in LaTex about developed components can be found here.
All components code is organized in directories with names that starts with "Esercizio*".