Third development card
Rev3
Rev3 includes a switch to the Xilinx ecosystem, for bigger, still manufactured, CPLDs and an introduction of SDRAM and Flash ROM.
I also added considerably more capacitors for the CPLD and CPUs plus a dual clock-mutliplier/crystal footprint and full-width address decoding on the CPLD. Full 32 bit level shifting for the data bus interfaces to the RAM.
Five status LEDs are added for the pure opulent indulgence of things. There are still eleven test pins remaining for bodging.
After a lot of firmware development DFB1r3 has achieved:
- 16MHz mode
- 50MHz mode
- 128MB AltRAM
- DSP working
- Onboard FPU supported
- Software-flashable 16-bit fast ROM
- 'Stock' mode, where all but the flash is disabled and the Falcon runs with on-board resources only
The board is, however, too large to fit in the case with the PSU or top shielding in place. This is because almost all signals are broken out for testing and development.
The clock lines have needed some bodge wires to insert some in-series termination and I completely forgot the STERM line! I experimented with a PLL clock-multiplier instead of a crystal oscillator too, but I wasn't happy with the results.
Revision 4, therefore, will look to fit with the stock PSU in place, provide inline termination for all clock lines, actually connect up STERM(!) and remove the PLL.
I'll also look to improve wiring of the SDRAM to reduce CPLD usage (the current 288 macrocell one is very expensive), possibly investigate splitting logic across two, lower cost CPLDs and look into providing an onboard FPU as well. Experiments for the latter are underway with a rev3 'hat'...
