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Merge pull request #300 from diffblue/verilog-let
Verilog: let
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Original file line number | Diff line number | Diff line change |
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CORE | ||
let1.sv | ||
--bound 0 | ||
^EXIT=0$ | ||
^SIGNAL=0$ | ||
-- | ||
^warning: ignoring |
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// The "let construct" was introduced by SystemVerilog 1800-2009. | ||
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module main; | ||
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let some_let = 8'd123; | ||
p0: assert property (some_let == 123 && $bits(some_let) == 8); | ||
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// The standard doesn't say, but we allow these to be elaboration-time | ||
// constants. | ||
parameter some_parameter = some_let; | ||
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p1: assert property (some_parameter == 123 && $bits(some_parameter) == 8); | ||
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// May depend on state. | ||
wire some_wire; | ||
let some_let_eq_wire = some_wire; | ||
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p2: assert property (some_let_eq_wire == some_wire); | ||
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endmodule |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,8 @@ | ||
CORE | ||
let_ports1.sv | ||
--bound 0 | ||
^file .* line 5: let ports not supported yet$ | ||
^EXIT=2$ | ||
^SIGNAL=0$ | ||
-- | ||
^warning: ignoring |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,8 @@ | ||
// The "let construct" was introduced by SystemVerilog 1800-2009. | ||
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module main; | ||
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let some_let_with_port(x) = x + 1; | ||
p0: assert property (some_let_with_port(1) == 2); | ||
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endmodule |
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