Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Verilog: fix for indexed part select #424

Draft
wants to merge 1 commit into
base: main
Choose a base branch
from
Draft

Verilog: fix for indexed part select #424

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 2 additions & 1 deletion src/verilog/verilog_typecheck_expr.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2411,7 +2411,6 @@ exprt verilog_typecheck_exprt::convert_trinary_expr(ternary_exprt expr)

// The index need not be a constant.
exprt &op1 = expr.op1();
convert_expr(op1);

// The width of the indexed part select must be an
// elaboration-time constant.
Expand Down Expand Up @@ -2455,6 +2454,8 @@ exprt verilog_typecheck_exprt::convert_trinary_expr(ternary_exprt expr)
else
{
// Index not constant.
convert_expr(op1);

// Use logical right-shift followed by (constant) extractbits.
auto op1_adjusted =
minus_exprt{op1, from_integer(op0_offset, op1.type())};
Expand Down