Verilog: compilation-unit scope

src/verilog/parser.y

@@ -603,6 +603,7 @@ description:
  	| program_declaration
  	| package_declaration
 	| attribute_instance_brace package_item
+		{ PARSER.parse_tree.create_package_item(std::move(stack_expr($2))); }
  	| attribute_instance_brace bind_directive
  	| config_declaration
         ;

src/verilog/verilog_parse_tree.cpp

@@ -52,6 +52,25 @@ void verilog_parse_treet::create_module(
 
 /*******************************************************************\
 
+Function: verilog_parse_treet::create_package_item
+
+  Inputs:
+
+ Outputs:
+
+ Purpose:
+
+\*******************************************************************/
+
+void verilog_parse_treet::create_package_item(exprt package_item)
+{
+  items.push_back(itemt());
+  items.back().type = itemt::PACKAGE_ITEM;
+  items.back().package_item = std::move(package_item);
+}
+
+/*******************************************************************\
+
 Function: verilog_parse_treet::modules_provided
 
   Inputs:
@@ -135,9 +154,9 @@ void verilog_parse_treet::itemt::show(std::ostream &out) const
   case itemt::MODULE:
     verilog_module.show(out);
     break;
-    
-  case itemt::TYPEDEF:
-    verilog_typedef.show(out);
+
+  case itemt::PACKAGE_ITEM:
+    out << "Package item: " << package_item.pretty() << '\n';
     break;
 
   default:

src/verilog/verilog_parse_tree.h

@@ -22,34 +22,41 @@ class verilog_parse_treet
   class verilog_typedeft
   {
   public:
-    typet symbol;
+    irept declarator;
     typet type;
 
     void show(std::ostream &out) const
     {
       out << "Typedef:\n";
-      out << "\n";
+      out << "  " << declarator.get(ID_base_name) << " = " << type.pretty()
+          << '\n';
     }
   };
 
   struct itemt
   {
   public:
-    typedef enum { MODULE, TYPEDEF } item_typet;
+    // package items are functions, tasks, typedefs, variables,
+    // nets, variables, parameters
+    typedef enum
+    {
+      MODULE,
+      PACKAGE_ITEM
+    } item_typet;
     item_typet type;
 
     verilog_modulet verilog_module;
-    
-    verilog_typedeft verilog_typedef;
-    
+
+    exprt package_item;
+
     bool is_module() const
     {
       return type==MODULE;
     }
 
-    bool is_typedef() const
+    bool is_package_item() const
     {
-      return type==TYPEDEF;
+      return type == PACKAGE_ITEM;
     }
 
     void show(std::ostream &out) const;
@@ -80,14 +87,8 @@ class verilog_parse_treet
     exprt &ports,
     exprt &statements);
 
-  void create_typedef(irept &declaration)
-  {
-    items.push_back(itemt());
-    items.back().type=itemt::TYPEDEF;
-    items.back().verilog_typedef.symbol.swap(declaration.get_sub()[0]);
-    items.back().verilog_typedef.type.swap(declaration.add(ID_type));
-  }
-
+  void create_package_item(exprt);
+
   void swap(verilog_parse_treet &parse_tree)
   {
     parse_tree.items.swap(items);