Improve debug and atomics, read CPU ID from CSR

src/platform/riscv32/qemu32_virt/asm/atomics.s

@@ -28,7 +28,7 @@ acquire_attempt:
 # Release a simple lock that we've already held
 # => a0 = memory address of spin lock to release
 release_spin_lock:
-  amoswap.w.rl x0, x0, (a0)     # release lock by atomically writing 0 to it
+  amoswap.w.rl  x0, x0, (a0)    # release lock by atomically writing 0 to it
   ret
 
 # Acquire a spin lock to write to the serial debug port

src/platform/riscv32/qemu32_virt/asm/utils.s

@@ -0,0 +1,13 @@
+# kernel low-level utility code for Qemu Virt hardware environment
+#
+# (c) Chris Williams, 2018.
+# See LICENSE for usage and copying.
+
+.section .text
+.global platform_get_cpu_id
+
+# Look up the running core's ID
+# <= a0 = CPU core / hart ID
+platform_get_cpu_id:
+  csrrc a0, mhartid, x0
+  ret

src/platform/riscv32/sifive_u34/asm/utils.s

@@ -0,0 +1,13 @@
+# kernel low-level utility code for SiFive U34 hardware
+#
+# (c) Chris Williams, 2018.
+# See LICENSE for usage and copying.
+
+.section .text
+.global platform_get_cpu_id
+
+# Look up the running core's ID
+# <= a0 = CPU core / hart ID
+platform_get_cpu_id:
+  csrrc a0, mhartid, x0
+  ret