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Interpreter_LoadStore: Generate alignment exceptions if lmw, lswi, lswx, stmw, stswi, or stswx is executed when the MSR[LE] bit is set #6592

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merged 1 commit into from Apr 4, 2018

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@lioncash lioncash commented Apr 4, 2018

This is required by the architecture specification

@lioncash lioncash changed the title Interpreter_LoadStore: Generate alignment exceptions if the MSR[LE] bit is set when executing lmw, lswi, lswx, stmw, stswi, or stswx Interpreter_LoadStore: Generate alignment exceptions if lmw, lswi, lswx, stmw, stswi, or stswx is executed when the MSR[LE] bit is set Apr 4, 2018
…wx, stmw, stswi, or stswx is executed when the MSR[LE] bit is set

Improves exception accuracy regarding an admittedly very unlikely
scenario.
@@ -213,7 +213,7 @@ void Interpreter::lmw(UGeckoInstruction inst)
{
u32 address = Helper_Get_EA(inst);

if ((address & 0b11) != 0)
if ((address & 0b11) != 0 || UReg_MSR{MSR}.LE)

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@@ -241,7 +241,7 @@ void Interpreter::stmw(UGeckoInstruction inst)
{
u32 address = Helper_Get_EA(inst);

if ((address & 0b11) != 0)
if ((address & 0b11) != 0 || UReg_MSR{MSR}.LE)

This comment was marked as off-topic.

@degasus degasus merged commit ba42238 into dolphin-emu:master Apr 4, 2018
@lioncash lioncash deleted the imagine-le-ppc branch April 4, 2018 11:46
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