Interpreter_FPUtils: Set FPSCR.VXSNAN if either operand to NI_mul() is a signaling NaN

[lioncash]

If either of the operands are signaling NaNs, then an invalid operation exception needs to be indicated within the FPSCR.

This corrects SNaN flag setting for fmul, fmuls, ps_mul, ps_muls0, and ps_muls1.

[BhaaLseN]

Reading the architecture manual seems to be hard; I can only see those put in words next to fcmp etc. (not fmul etc.); but at the same time they are said to affect VXSNAN.
I'm trusting you interpreting the manual the right way (as in: they should just do the same as fcmp); under that assumption the code looks good to me.

[JMC47]

Is able to boot/run games, so, appears not to break things.

[lioncash]

@BhaaLseN Yeah, the manual is kind of annoying (especially wrt pseudocode; I've been spoiled by ARMs manuals). However, in 3.3.6.1 (Invalid Operation and Zero Divide Exception Conditions) in PowerPC® Microprocessor Family: The Programming Environments Manual for 32 and 64-bit Microprocessors gives a better definition of operations, where it states a little further down:

An invalid operation exception occurs when an operand is invalid for the specified operation. The invalid operations are as follows:

• Any operation except load, store, move, select, or mtfsf on a signaling NaN (SNaN)

(other bullet points omitted since they aren't relevant).

Any instruction that does specific things with NaNs that don't adhere to that (and any other following bullet points about NaNs) indicate them in their description (like fabs and fnabs for instance)