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Restored VPLL freq table! @gokhanmoral Legacy will live AGAIN! 520Mhz…
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… Online!

Now we can use 108,330,440,520 Mhz for GPU freq! and 520Mhz with 1350mV now STABLE!

i get 29.7~30 FPS in Heavy 3D Bench apps, and Great performance in games!

Get ready to paly in freezer as device is HOT, but hell that is awesome!
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@dorimanx
dorimanx committed Nov 28, 2013
1 parent f8f3a01 commit a90b0f4
Showing 1 changed file with 58 additions and 20 deletions.
78 changes: 58 additions & 20 deletions drivers/gpu/mali400/r3p2/mali/platform/pegasus-m400/exynos4_pmm.c
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Expand Up @@ -79,7 +79,7 @@ typedef struct mali_dvfs_stepTag{
}mali_dvfs_step;

mali_dvfs_step step[MALI_DVFS_STEPS]={
/*step 0 clk*/ {100, 950000},
/*step 0 clk*/ {108, 950000},
/*step 1 clk*/ {160, 950000},
/*step 2 clk*/ {200, 1000000},
/*step 3 clk*/ {266, 1050000},
Expand All @@ -94,7 +94,7 @@ mali_dvfs_staycount_table mali_dvfs_staycount[MALI_DVFS_STEPS]={
/*step 4*/{0}
};

int step0_clk = 100;
int step0_clk = 108;
int step0_vol = 950000;
int step1_clk = 160;
int step1_vol = 950000;
Expand All @@ -114,14 +114,14 @@ int step3_up = 85;
int step4_down = 70;

mali_dvfs_table mali_dvfs_all[MAX_MALI_DVFS_STEPS]={
{100 ,1000000 , 950000},
{108 ,1000000 , 950000},
{160 ,1000000 , 950000},
{200 ,1000000 , 1000000},
{266 ,1000000 , 1050000},
{266 ,1000000 , 1050000} };

mali_dvfs_table mali_dvfs[MALI_DVFS_STEPS]={
{100 ,1000000 , 950000},
{108 ,1000000 , 950000},
{160 ,1000000 , 950000},
{200 ,1000000 ,1000000},
{266 ,1000000 ,1050000},
Expand Down Expand Up @@ -156,7 +156,7 @@ mali_runtime_resume_table mali_runtime_resume = {160, 950000, 1};
#define ASV_5_LEVEL 5

static unsigned int asv_3d_volt_5_table[ASV_5_LEVEL][MALI_DVFS_STEPS] = {
/* L4(100MHz), L3(160MHz), L2(266MHz), L1(330MHz) */
/* L4(108MHz), L3(160MHz), L2(266MHz), L1(330MHz) */
{ 950000, 1000000, 1100000, 1150000, 1200000}, /* S */
{ 950000, 1000000, 1100000, 1150000, 1200000}, /* A */
{ 900000, 950000, 1000000, 1100000, 1200000}, /* B */
Expand Down Expand Up @@ -200,8 +200,9 @@ static struct clk *mali_mout0_clock = NULL;
static struct clk *mali_clock = NULL;

/* Orion */
static const mali_bool bis_vpll = MALI_FALSE;
int mali_gpu_clk = 100;
extern int mali_use_vpll;

int mali_gpu_clk = 108;
int mali_gpu_vol = 950000;

static unsigned int GPU_MHZ = 1000000;
Expand Down Expand Up @@ -255,6 +256,7 @@ void mali_regulator_disable(void)
return;
}
regulator_disable(g3d_regulator);
bPoweroff = 1;
}

void mali_regulator_enable(void)
Expand All @@ -264,6 +266,7 @@ void mali_regulator_enable(void)
return;
}
regulator_enable(g3d_regulator);
bPoweroff = 0;
}

void mali_regulator_set_voltage(int min_uV, int max_uV)
Expand Down Expand Up @@ -293,15 +296,16 @@ static unsigned int get_mali_dvfs_status(void)
return maliDvfsStatus.currentStep;
}

mali_bool mali_clk_get(void)
mali_bool mali_clk_get(mali_bool bis_vpll)
{
if (bis_vpll) {
if (bis_vpll == MALI_TRUE) {
if (ext_xtal_clock == NULL) {
ext_xtal_clock = clk_get(NULL, EXTXTALCLK_NAME);
if (IS_ERR(ext_xtal_clock)) {
MALI_PRINT(("MALI Error : failed to get source ext_xtal_clock\n"));
return MALI_FALSE;
}
clk_enable(ext_xtal_clock);
}

if (vpll_src_clock == NULL) {
Expand All @@ -310,6 +314,7 @@ mali_bool mali_clk_get(void)
MALI_PRINT(("MALI Error : failed to get source vpll_src_clock\n"));
return MALI_FALSE;
}
clk_enable(vpll_src_clock);
}

if (fout_vpll_clock == NULL) {
Expand All @@ -318,6 +323,7 @@ mali_bool mali_clk_get(void)
MALI_PRINT(("MALI Error : failed to get source fout_vpll_clock\n"));
return MALI_FALSE;
}
clk_enable(fout_vpll_clock);
}

if (sclk_vpll_clock == NULL) {
Expand All @@ -326,6 +332,7 @@ mali_bool mali_clk_get(void)
MALI_PRINT(("MALI Error : failed to get source sclk_vpll_clock\n"));
return MALI_FALSE;
}
clk_enable(sclk_vpll_clock);
}

if (mali_parent_clock == NULL) {
Expand All @@ -335,6 +342,7 @@ mali_bool mali_clk_get(void)
MALI_PRINT(( "MALI Error : failed to get source mali parent clock\n"));
return MALI_FALSE;
}
clk_enable(mali_parent_clock);
}

if (mali_mout0_clock == NULL) {
Expand Down Expand Up @@ -422,17 +430,19 @@ void mali_clk_put(mali_bool binc_mali_clock)
}
}

void mali_clk_set_rate(unsigned int clk, unsigned int mhz)
mali_bool mali_clk_set_rate(unsigned int clk, unsigned int mhz)
{
mali_bool bis_vpll = mali_use_vpll;

int err;
unsigned long rate = (unsigned long)clk * (unsigned long)mhz;

_mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
MALI_DEBUG_PRINT(3, ("Mali platform: Setting frequency to %d mhz\n", clk));

if (mali_clk_get() == MALI_FALSE) {
_mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
return;
if (mali_clk_get(bis_vpll) == MALI_FALSE) {
_mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
return MALI_FALSE;
}

if (bis_vpll) {
Expand All @@ -450,7 +460,7 @@ void mali_clk_set_rate(unsigned int clk, unsigned int mhz)
if (atomic_read(&clk_active) == 0) {
if (clk_enable(mali_clock) < 0) {
_mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
return;
return MALI_FALSE;
}
atomic_set(&clk_active, 1);
}
Expand All @@ -461,13 +471,19 @@ void mali_clk_set_rate(unsigned int clk, unsigned int mhz)

rate = mali_clk_get_rate();

if (bis_vpll)
mali_gpu_clk = (int)(rate / mhz);
else
mali_gpu_clk = (int)((rate + 500000) / mhz);

MALI_DEBUG_PRINT(1, ("Mali frequency %d\n", rate / mhz));
GPU_MHZ = mhz;
mali_gpu_clk = (int)(rate / mhz);

mali_clk_put(MALI_FALSE);

_mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);

return MALI_TRUE;
}

int get_mali_dvfs_control_status(void)
Expand Down Expand Up @@ -878,8 +894,7 @@ mali_bool mali_dvfs_handler(unsigned int utilization)
static mali_bool init_mali_clock(void)
{
mali_bool ret = MALI_TRUE;
gpu_power_state = 1;
bPoweroff = 1;
mali_bool bis_vpll = mali_use_vpll;

if (mali_clock != 0)
return ret; /* already initialized */
Expand All @@ -889,8 +904,9 @@ static mali_bool init_mali_clock(void)
if (mali_dvfs_lock == NULL)
return _MALI_OSK_ERR_FAULT;

if (!mali_clk_get()) {
if (!mali_clk_get(bis_vpll)) {
MALI_PRINT(("Error: Failed to get Mali clock\n"));
ret = MALI_FALSE;
goto err_clk;
}

Expand Down Expand Up @@ -922,6 +938,9 @@ static mali_bool init_mali_clock(void)

mali_clk_put(MALI_FALSE);

gpu_power_state = 0;
bPoweroff = 1;

return MALI_TRUE;

#ifdef CONFIG_REGULATOR
Expand Down Expand Up @@ -959,7 +978,6 @@ static _mali_osk_errcode_t enable_mali_clocks(void)
err = clk_enable(mali_clock);
MALI_DEBUG_PRINT(3,("enable_mali_clocks mali_clock %p error %d \n", mali_clock, err));
atomic_set(&clk_active, 1);
gpu_power_state = 1;
}

mali_runtime_resume.vol = mali_dvfs_get_vol(MALI_DVFS_STEPS + 1);
Expand Down Expand Up @@ -996,7 +1014,6 @@ static _mali_osk_errcode_t disable_mali_clocks(void)
if (atomic_read(&clk_active) == 1) {
clk_disable(mali_clock);
atomic_set(&clk_active, 0);
gpu_power_state = 0;
}
MALI_DEBUG_PRINT(3,("disable_mali_clocks mali_clock %p \n", mali_clock));

Expand Down Expand Up @@ -1084,6 +1101,9 @@ _mali_osk_errcode_t mali_platform_deinit(struct device *dev)
MALI_SUCCESS;
}

void mali_force_mpll(void);
void mali_restore_vpll_mode(void);

_mali_osk_errcode_t mali_platform_power_mode_change(struct device *dev, mali_power_mode power_mode)
{
switch (power_mode) {
Expand All @@ -1096,6 +1116,8 @@ _mali_osk_errcode_t mali_platform_power_mode_change(struct device *dev, mali_pow
#endif
MALI_DEBUG_PRINT(4,("enable clock \n"));
enable_mali_clocks();
mali_restore_vpll_mode();
gpu_power_state = 1;
bPoweroff = 0;
}
break;
Expand All @@ -1105,10 +1127,12 @@ _mali_osk_errcode_t mali_platform_power_mode_change(struct device *dev, mali_pow
MALI_POWER_MODE_LIGHT_SLEEP ? "MALI_POWER_MODE_LIGHT_SLEEP" :
"MALI_POWER_MODE_DEEP_SLEEP", bPoweroff ? "already off" : "powering off"));
if (bPoweroff == 0) {
mali_force_mpll();
disable_mali_clocks();
#if !defined(CONFIG_PM_RUNTIME)
g3d_power_domain_control(0);
#endif
gpu_power_state = 0;
bPoweroff = 1;
}

Expand Down Expand Up @@ -1241,6 +1265,20 @@ int mali_voltage_lock_init(void)
MALI_SUCCESS;
}

int mali_use_vpll_save;
void mali_restore_vpll_mode(void)
{
mali_use_vpll = mali_use_vpll_save;
}

void mali_force_mpll(void)
{
mali_use_vpll_save = mali_use_vpll;
mali_use_vpll = false;
mali_regulator_set_voltage(mali_gpu_vol, mali_gpu_vol);
mali_clk_set_rate((unsigned int)mali_gpu_clk, GPU_MHZ);
}

int mali_vol_get_from_table(int vol)
{
int i;
Expand Down

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