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AVX10.1 API introduction in JIT #101938

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merged 22 commits into from
Jun 9, 2024

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khushal1996
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@khushal1996 khushal1996 commented May 6, 2024

This PR tracks addition of AVX10.1 APIs in libraries along with relevant template tests and intrinsics in JIT. It also captures usage of the new intrinsics in JIT during lowering.

@dotnet-issue-labeler dotnet-issue-labeler bot added area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI new-api-needs-documentation labels May 6, 2024
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Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

@dotnet-policy-service dotnet-policy-service bot added the community-contribution Indicates that the PR has been added by a community member label May 6, 2024
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
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@tannergooding
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Changes mostly look good to me. There's some stray changes that are conflicting with PRs that went in over the past couple days that need to be resolved and some potential cleanup, but I think this is just about ready to merge

@tannergooding
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CC. @dotnet/jit-contrib PR from Intel is ready for review and needs secondary sign-off.

I've given this a decently thorough review already and plan on giving it one more pass before sign-off, but it could definitely do with another pair of eyes.

@JulieLeeMSFT
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@EgorBo please review the PR for AVX10.1.

@JulieLeeMSFT JulieLeeMSFT requested a review from EgorBo June 5, 2024 23:28

retNode =
gtNewSimdHWIntrinsicNode(TYP_SIMD16, op1, op2, op3, NI_FMA_MultiplyAddScalar, callJitType, 16);
GenTree* op3 = gtNewSimdCreateScalarUnsafeNode(TYP_SIMD16, impPopStack().val, callJitType, 16);
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why do we remove impImplicitR4orR8Cast from here?

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Looks like a merge error when rebasing. cleared it up to what it was.

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EgorBo commented Jun 6, 2024

@MihuBot

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I think the RyuJIT side is ok with the Tanner's comments. Do we want to run some ISA outerloops?

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EgorBo commented Jun 6, 2024

Any idea why this PR causes big diffs on an Intel cpu (must be some Skylake/Cascade Lake cpu on Azure): MihuBot/runtime-utils#403 ? I presume it's supposed to be no-op

@DeepakRajendrakumaran
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Any idea why this PR causes big diffs on an Intel cpu (must be some Skylake/Cascade Lake cpu on Azure): MihuBot/runtime-utils#403 ? I presume it's supposed to be no-op

Something is off here. We are not inlining the Vector512 method in some of these and resorting to software fallback

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Any idea why this PR causes big diffs on an Intel cpu (must be some Skylake/Cascade Lake cpu on Azure): MihuBot/runtime-utils#403 ? I presume it's supposed to be no-op

Something is off here. We are not inlining the Vector512 method in some of these and resorting to software fallback

There is a bug in there re ordering of flags being set. It got introduced when we added _EVEX flag. Will add a fix today

…rmatting adn resolve errors introduced when merging with main
@khushal1996
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khushal1996 commented Jun 7, 2024

Any idea why this PR causes big diffs on an Intel cpu (must be some Skylake/Cascade Lake cpu on Azure): MihuBot/runtime-utils#403 ? I presume it's supposed to be no-op

@EgorBo I have pushed a fix and here are the diffs

Ice lake
image

Cascade Lake
image

@tannergooding tannergooding merged commit b5948bf into dotnet:main Jun 9, 2024
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6 participants