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SVE: Added Load2xVectorAndUnzip, Load3xVectorAndUnzip, Load4xVectorAndUnzip APIs #102180

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merged 24 commits into from
May 29, 2024
Merged

SVE: Added Load2xVectorAndUnzip, Load3xVectorAndUnzip, Load4xVectorAndUnzip APIs #102180

merged 24 commits into from
May 29, 2024

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TIHan
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@TIHan TIHan commented May 13, 2024 •
edited

Contributes to #99957

Adds:

  • Load2xVectorAndUnzip
  • Load3xVectorAndUnzip
  • Load4xVectorAndUnzip

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Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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Tagging subscribers to this area: @dotnet/area-system-runtime-intrinsics
See info in area-owners.md if you want to be subscribed.

@kunalspathak kunalspathak added the arm-sve Work related to arm64 SVE/SVE2 support label May 14, 2024
@build-analysis build-analysis bot mentioned this pull request May 14, 2024
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kunalspathak requested changes May 14, 2024
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can you also follow the instructions at #99957 (comment) and confirm if all the newly added tests pass? I can work with you on machine where you can run these tests.

src/tests/JIT/HardwareIntrinsics/Arm/Shared/SveLoadVectorx2Test.template Outdated Show resolved Hide resolved
src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs Show resolved Hide resolved
src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs Outdated Show resolved Hide resolved
@kunalspathak kunalspathak mentioned this pull request May 14, 2024
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TIHan commented May 14, 2024

The tests don't pass right now, but I think the fix your suggesting will work.

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TIHan commented May 14, 2024 •
edited

Tests pass now:

Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:29.989 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_float()
12:42:29.993 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_double()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.006 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_double()
12:42:30.011 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_sbyte()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.023 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_sbyte()
12:42:30.028 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_short()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.041 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_short()
12:42:30.046 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_int()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.058 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_int()
12:42:30.063 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_long()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.076 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_long()
12:42:30.080 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_byte()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.094 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_byte()
12:42:30.098 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ushort()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.111 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ushort()
12:42:30.115 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_uint()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.129 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_uint()
12:42:30.133 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ulong()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.146 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ulong()
12:42:30.150 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_float()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.164 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_float()
12:42:30.169 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_double()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.182 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_double()
12:42:30.187 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_sbyte()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.201 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_sbyte()
12:42:30.205 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_short()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.220 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_short()
12:42:30.224 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_int()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.238 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_int()
12:42:30.242 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_long()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.256 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_long()
12:42:30.260 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_byte()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.274 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_byte()
12:42:30.278 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ushort()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.293 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ushort()
12:42:30.297 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_uint()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.311 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_uint()
12:42:30.315 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ulong()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.329 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ulong()
12:42:30.334 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_float()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.348 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_float()
12:42:30.353 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_double()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.367 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_double()
12:42:30.372 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_sbyte()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.386 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_sbyte()
12:42:30.390 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_short()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.405 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_short()
12:42:30.409 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_int()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.423 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_int()
12:42:30.428 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_long()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.442 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_long()
12:42:30.446 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_byte()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.461 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_byte()
12:42:30.465 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ushort()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.480 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ushort()
12:42:30.484 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_uint()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.499 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_uint()
12:42:30.503 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ulong()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:42:30.517 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ulong()

12:48:49.964 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_float()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:49.978 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_float()
12:48:49.982 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_double()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:49.995 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_double()
12:48:50.000 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_sbyte()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.012 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_sbyte()
12:48:50.017 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_short()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.030 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_short()
12:48:50.035 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_int()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.047 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_int()
12:48:50.052 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_long()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.064 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_long()
12:48:50.069 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_byte()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.081 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_byte()
12:48:50.086 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ushort()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.098 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ushort()
12:48:50.103 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_uint()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.115 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_uint()
12:48:50.120 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ulong()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.133 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ulong()
12:48:50.138 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_float()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.151 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_float()
12:48:50.156 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_double()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.169 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_double()
12:48:50.173 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_sbyte()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.186 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_sbyte()
12:48:50.191 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_short()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.204 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_short()
12:48:50.209 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_int()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.221 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_int()
12:48:50.226 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_long()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.238 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_long()
12:48:50.243 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_byte()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.256 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_byte()
12:48:50.261 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ushort()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.275 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ushort()
12:48:50.280 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_uint()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.293 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_uint()
12:48:50.298 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ulong()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.311 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ulong()
12:48:50.316 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_float()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.330 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_float()
12:48:50.334 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_double()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.348 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_double()
12:48:50.353 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_sbyte()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.366 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_sbyte()
12:48:50.371 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_short()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.384 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_short()
12:48:50.389 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_int()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.402 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_int()
12:48:50.407 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_long()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.420 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_long()
12:48:50.425 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_byte()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.439 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_byte()
12:48:50.443 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ushort()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.457 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ushort()
12:48:50.461 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_uint()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.475 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_uint()
12:48:50.479 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ulong()
Beginning scenario: RunUnsupportedScenario
Beginning scenario: RunClassFldScenario
12:48:50.492 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ulong()

@kunalspathak
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Tests pass now:

It is running just the RunUnsupportedScenario. You need to verify this on a arm64 machine that supports SVE feature.

@TIHan
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TIHan commented May 14, 2024

Gotcha. Will need to find an arm64 machine that supports it then.

@build-analysis build-analysis bot mentioned this pull request May 15, 2024
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@TIHan
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TIHan commented May 16, 2024

@dotnet/arm64-contrib @kunalspathak this is ready. Had to play whack-a-mole.

Tests are passing and running :)

19:23:36.975 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_float()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:36.999 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_float()
19:23:37.002 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_double()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.021 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_double()
19:23:37.025 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_sbyte()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.043 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_sbyte()
19:23:37.046 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_short()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.065 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_short()
19:23:37.068 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_int()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.087 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_int()
19:23:37.091 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_long()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.110 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_long()
19:23:37.113 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_byte()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.132 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_byte()
19:23:37.135 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ushort()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.154 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ushort()
19:23:37.158 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_uint()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.176 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_uint()
19:23:37.180 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ulong()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.198 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ulong()
19:23:37.202 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_float()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.227 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_float()
19:23:37.230 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_double()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.250 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_double()
19:23:37.253 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_sbyte()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.273 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_sbyte()
19:23:37.277 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_short()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.296 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_short()
19:23:37.300 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_int()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.320 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_int()
19:23:37.323 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_long()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.343 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_long()
19:23:37.346 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_byte()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.366 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_byte()
19:23:37.370 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ushort()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.390 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ushort()
19:23:37.394 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_uint()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.414 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_uint()
19:23:37.418 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ulong()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.438 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ulong()
19:23:37.441 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_float()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.469 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_float()
19:23:37.472 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_double()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.493 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_double()
19:23:37.497 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_sbyte()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.518 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_sbyte()
19:23:37.522 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_short()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.543 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_short()
19:23:37.546 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_int()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.567 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_int()
19:23:37.570 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_long()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.591 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_long()
19:23:37.595 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_byte()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.616 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_byte()
19:23:37.619 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ushort()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.640 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ushort()
19:23:37.643 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_uint()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.665 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_uint()
19:23:37.668 Running test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ulong()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:23:37.690 Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ulong()


19:35:41.168 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_float()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.190 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_float()
19:35:41.194 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_double()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.211 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_double()
19:35:41.214 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_sbyte()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.231 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_sbyte()
19:35:41.234 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_short()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.251 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_short()
19:35:41.254 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_int()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.271 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_int()
19:35:41.274 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_long()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.290 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_long()
19:35:41.294 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_byte()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.311 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_byte()
19:35:41.314 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ushort()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.331 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ushort()
19:35:41.334 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_uint()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.351 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_uint()
19:35:41.354 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ulong()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.371 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx2_ulong()
19:35:41.375 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_float()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.398 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_float()
19:35:41.401 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_double()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.419 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_double()
19:35:41.423 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_sbyte()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.440 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_sbyte()
19:35:41.443 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_short()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.461 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_short()
19:35:41.464 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_int()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.482 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_int()
19:35:41.486 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_long()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.503 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_long()
19:35:41.506 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_byte()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.524 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_byte()
19:35:41.527 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ushort()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.545 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ushort()
19:35:41.548 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_uint()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.566 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_uint()
19:35:41.569 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ulong()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.587 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx3_ulong()
19:35:41.590 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_float()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.617 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_float()
19:35:41.620 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_double()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.639 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_double()
19:35:41.643 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_sbyte()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.661 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_sbyte()
19:35:41.664 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_short()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.683 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_short()
19:35:41.686 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_int()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.705 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_int()
19:35:41.708 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_long()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.726 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_long()
19:35:41.730 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_byte()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.748 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_byte()
19:35:41.752 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ushort()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.770 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ushort()
19:35:41.774 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_uint()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.792 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_uint()
19:35:41.796 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ulong()
Beginning scenario: RunBasicScenario
Beginning scenario: RunReflectionScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
19:35:41.815 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_LoadVectorx4_ulong()

@TIHan TIHan marked this pull request as ready for review May 16, 2024 02:41
@a74nh a74nh mentioned this pull request May 16, 2024
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@kunalspathak kunalspathak mentioned this pull request May 16, 2024
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kunalspathak
kunalspathak requested changes May 16, 2024
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Please update the API names to Load2xVectorAndUnzip.

src/coreclr/jit/hwintrinsicarm64.cpp Outdated Show resolved Hide resolved
src/coreclr/jit/hwintrinsiclistarm64sve.h Outdated Show resolved Hide resolved
src/coreclr/jit/lsraarm64.cpp Outdated
@@ -1758,6 +1758,18 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree, int* pDstCou
break;
}

case NI_Sve_LoadVectorx2:
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this can be combined with above cases:

            case NI_Sve_LoadVectorx2:
            case NI_Sve_LoadVectorx3:
            case NI_Sve_LoadVectorx4:
                assert(intrin.op2 != nullptr);
                srcCount += BuildOperandUses(intrin.op2);
                FALLTHROUGH;
            case NI_AdvSimd_LoadVector64x2AndUnzip:
            case NI_AdvSimd_LoadVector64x3AndUnzip:
            case NI_AdvSimd_LoadVector64x4AndUnzip:
            case NI_AdvSimd_Arm64_LoadVector128x2AndUnzip:
            case NI_AdvSimd_Arm64_LoadVector128x3AndUnzip:
            case NI_AdvSimd_Arm64_LoadVector128x4AndUnzip:
            case NI_AdvSimd_LoadVector64x2:
            case NI_AdvSimd_LoadVector64x3:
            case NI_AdvSimd_LoadVector64x4:
            case NI_AdvSimd_Arm64_LoadVector128x2:
            case NI_AdvSimd_Arm64_LoadVector128x3:
            case NI_AdvSimd_Arm64_LoadVector128x4:
            case NI_AdvSimd_LoadAndReplicateToVector64x2:
            case NI_AdvSimd_LoadAndReplicateToVector64x3:
            case NI_AdvSimd_LoadAndReplicateToVector64x4:
            case NI_AdvSimd_Arm64_LoadAndReplicateToVector128x2:
            case NI_AdvSimd_Arm64_LoadAndReplicateToVector128x3:
            case NI_AdvSimd_Arm64_LoadAndReplicateToVector128x4:
            {
                assert(intrin.op1 != nullptr);
                BuildConsecutiveRegistersForDef(intrinsicTree, dstCount);
                *pDstCount = dstCount;
                break;
            }

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This is still not resolved.

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I can't do this as a fallthrough because there is another fallthrough above it.

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yes, never mind.

src/coreclr/jit/gentree.cpp Show resolved Hide resolved
src/tests/JIT/HardwareIntrinsics/Arm/Shared/SveLoadVectorx2Test.template Outdated Show resolved Hide resolved
src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs Outdated Show resolved Hide resolved
@TIHan TIHan changed the title SVE: Added LoadVectorx2, LoadVectorx3, LoadVectorx4 APIs SVE: Added Load2xVectorAndUnzip, Load3xVectorAndUnzip, Load4xVectorAndUnzip APIs May 17, 2024
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TIHan commented May 18, 2024

Stress modes are failing badly for the ro once I fixed the stress tester to pass the env variables. Will be looking into it.

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TIHan commented May 21, 2024

Having some failures with Load2xVector and Load3xVector in stress testing; the results are coming back as zeroes for RunClassFldScenario. I think the use of the instruction itself is fine, but something is not handling setting _fld1 and _fld2 correctly:

        public void RunClassFldScenario()
        {
            TestLibrary.TestFramework.BeginScenario(nameof(RunClassFldScenario));
 
            //TODO-SVE: Once register allocation exists for predicates, move loadMask into DataTable
            {Op1VectorType}<{Op1BaseType}> loadMask = Sve.CreateTrueMask{RetBaseType}(SveMaskPattern.All);
 
            (_fld1, _fld2) = {Isa}.{Method}(loadMask, ({Op1BaseType}*)_dataTable.inArrayPtr);
 
            ValidateResult(_fld1, _fld2, _dataTable.inArrayPtr);
        }

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TIHan commented May 25, 2024

@kunalspathak this is ready. I do get an assertion in the non_faulting cases under stress modes, but it appears to be related to INS_sve_str and/or INS_sve_ldr.

C:\Users\Administrator\Desktop\wills>py .\stress_tester.py %CORE_ROOT%/corerun.exe "C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\HardwareIntrinsics_Arm_ro.dll" Sve_Load2xVector
Starting test: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root/corerun.exe C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\HardwareIntrinsics_Arm_ro.dll Sve_Load2xVector
===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_float() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_double() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_sbyte() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_short() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_int() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_long() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_byte() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_ushort() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_uint() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_ulong() : 15
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
Test failed:
..........................................
..........................................
Sve.Load2xVectorAndUnzip(Vector<Double>): Load2xVectorAndUnzip failed:
 input: (0.6133104845872838, 0.7006695179412495, 0.12108935127421827, 0.8997330364358254)
 result1: (0, 0)
 result2: (0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_double() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load2xVectorAndUnzip.double.cs:line 62
   at Program.<<Main>$>g__TestExecutor2904|0_2905(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 72917
..........................................
Sve.Load2xVectorAndUnzip(Vector<SByte>): Load2xVectorAndUnzip failed:
 input: (5, 39, 35, 83, 60, 33, 63, 82, 106, 9, 73, 66, 22, 89, 30, 122, 8, 74, 25, 62, 96, 123, 29, 121, 68, 17, 13, 0, 98, 44, 26, 30)
 result1: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
 result2: (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_sbyte() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load2xVectorAndUnzip.sbyte.cs:line 62
   at Program.<<Main>$>g__TestExecutor2905|0_2906(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 72941
..........................................
Sve.Load2xVectorAndUnzip(Vector<UInt32>): Load2xVectorAndUnzip failed:
 input: (252894, 958381, 851962, 588773, 257679, 1047826, 524188, 557023)
 result1: (0, 0, 0, 0)
 result2: (0, 0, 0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_uint() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load2xVectorAndUnzip.uint.cs:line 62
   at Program.<<Main>$>g__TestExecutor2911|0_2912(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 73085
------------------- {'JitStress': '2'} -------------------
Test failed:
..........................................
..........................................
Sve.Load2xVectorAndUnzip(Vector<Int16>): Load2xVectorAndUnzip failed:
 input: (5478, 28930, 17994, 6432, 21248, 20597, 7756, 29592, 28337, 31570, 9430, 24677, 19207, 5547, 14547, 30285)
 result1: (0, 0, 0, 0, 0, 0, 0, 0)
 result2: (0, 0, 0, 0, 0, 0, 0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_short() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load2xVectorAndUnzip.short.cs:line 62
   at Program.<<Main>$>g__TestExecutor2906|0_2907(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 72965
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
Test failed:
..........................................
..........................................
Sve.Load2xVectorAndUnzip(Vector<Int16>): Load2xVectorAndUnzip failed:
 input: (21359, 31653, 17921, 19974, 25456, 12419, 23928, 14937, 8301, 9166, 31608, 3141, 8987, 7828, 19614, 12115)
 result1: (0, 0, 0, 0, 0, 0, 0, 0)
 result2: (0, 0, 0, 0, 0, 0, 0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_short() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load2xVectorAndUnzip.short.cs:line 62
   at Program.<<Main>$>g__TestExecutor2906|0_2907(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 72965
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
Test failed:
..........................................
..........................................
Sve.Load2xVectorAndUnzip(Vector<Int16>): Load2xVectorAndUnzip failed:
 input: (12196, 18409, 4292, 24881, 16536, 31377, 28051, 3158, 8410, 22701, 31639, 6207, 18211, 20802, 4742, 19213)
 result1: (0, 0, 0, 0, 0, 0, 0, 0)
 result2: (0, 0, 0, 0, 0, 0, 0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_short() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load2xVectorAndUnzip.short.cs:line 62
   at Program.<<Main>$>g__TestExecutor2906|0_2907(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 72965
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
Test failed:
..........................................
..........................................
Sve.Load2xVectorAndUnzip(Vector<Int16>): Load2xVectorAndUnzip failed:
 input: (20364, 21600, 5779, 28558, 10589, 26888, 25382, 32497, 14728, 15334, 11642, 32280, 31665, 23636, 17358, 1647)
 result1: (0, 0, 0, 0, 0, 0, 0, 0)
 result2: (0, 0, 0, 0, 0, 0, 0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_short() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load2xVectorAndUnzip.short.cs:line 62
   at Program.<<Main>$>g__TestExecutor2906|0_2907(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 72965
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
Test failed:
..........................................
..........................................
Sve.Load2xVectorAndUnzip(Vector<Int16>): Load2xVectorAndUnzip failed:
 input: (13888, 12204, 8372, 15189, 30835, 1141, 27790, 326, 30719, 2279, 17830, 10053, 6842, 30193, 30221, 27613)
 result1: (0, 0, 0, 0, 0, 0, 0, 0)
 result2: (0, 0, 0, 0, 0, 0, 0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_short() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load2xVectorAndUnzip.short.cs:line 62
   at Program.<<Main>$>g__TestExecutor2906|0_2907(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 72965
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
Test failed:
..........................................
..........................................
Sve.Load2xVectorAndUnzip(Vector<Int16>): Load2xVectorAndUnzip failed:
 input: (11691, 12234, 4785, 5384, 14349, 7919, 10106, 13514, 32302, 13779, 3390, 3376, 17674, 25138, 2508, 29327)
 result1: (0, 0, 0, 0, 0, 0, 0, 0)
 result2: (0, 0, 0, 0, 0, 0, 0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_short() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load2xVectorAndUnzip.short.cs:line 62
   at Program.<<Main>$>g__TestExecutor2906|0_2907(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 72965
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
Test failed:
..........................................
..........................................
Sve.Load2xVectorAndUnzip(Vector<Int16>): Load2xVectorAndUnzip failed:
 input: (14345, 660, 16589, 24747, 26519, 20271, 1525, 6831, 21287, 10068, 28408, 30275, 8783, 23594, 30160, 18408)
 result1: (0, 0, 0, 0, 0, 0, 0, 0)
 result2: (0, 0, 0, 0, 0, 0, 0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_short() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load2xVectorAndUnzip.short.cs:line 62
   at Program.<<Main>$>g__TestExecutor2906|0_2907(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 72965
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
Test failed:
..........................................
..........................................
Sve.Load2xVectorAndUnzip(Vector<Int16>): Load2xVectorAndUnzip failed:
 input: (7214, 12548, 15356, 21152, 15335, 24596, 2787, 7306, 4961, 23822, 30251, 4176, 8614, 10203, 16002, 20497)
 result1: (0, 0, 0, 0, 0, 0, 0, 0)
 result2: (0, 0, 0, 0, 0, 0, 0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_short() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load2xVectorAndUnzip.short.cs:line 62
   at Program.<<Main>$>g__TestExecutor2906|0_2907(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 72965
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------
Test failed:
..........................................
..........................................
Sve.Load2xVectorAndUnzip(Vector<Int16>): Load2xVectorAndUnzip failed:
 input: (4839, 31774, 4576, 26386, 14024, 18208, 604, 23166, 15686, 20642, 27269, 4620, 467, 7183, 22499, 22141)
 result1: (0, 0, 0, 0, 0, 0, 0, 0)
 result2: (0, 0, 0, 0, 0, 0, 0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_short() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load2xVectorAndUnzip.short.cs:line 62
   at Program.<<Main>$>g__TestExecutor2906|0_2907(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 72965

C:\Users\Administrator\Desktop\wills>py .\stress_tester.py %CORE_ROOT%/corerun.exe "C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\HardwareIntrinsics_Arm_ro.dll" Sve_Load3xVector
Starting test: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root/corerun.exe C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\HardwareIntrinsics_Arm_ro.dll Sve_Load3xVector
===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_float() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_double() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_sbyte() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_short() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_int() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_long() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_byte() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_ushort() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_uint() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_ulong() : 15
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
Test failed:
..........................................
..........................................
Sve.Load3xVectorAndUnzip(Vector<UInt64>): Load3xVectorAndUnzip failed:
 input: (15645823607218712798, 572990044129563178, 3121102228919041761, 9265626275105266305, 9166453078434613902, 3868329873254078933)
 result1: (0, 0)
 result2: (0, 0)
 result3: (0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_ulong() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load3xVectorAndUnzip.ulong.cs:line 62
   at Program.<<Main>$>g__TestExecutor2922|0_2923(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 73349
------------------- {'JitStress': '2'} -------------------
Test failed:
..........................................
..........................................
Sve.Load3xVectorAndUnzip(Vector<UInt64>): Load3xVectorAndUnzip failed:
 input: (17037784512780989447, 9110950410660643019, 6355213098474630964, 11372029044526001873, 9867663135764182179, 8480366298396106710)
 result1: (0, 0)
 result2: (0, 0)
 result3: (0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_ulong() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load3xVectorAndUnzip.ulong.cs:line 62
   at Program.<<Main>$>g__TestExecutor2922|0_2923(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 73349
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
Test failed:
..........................................
..........................................
Sve.Load3xVectorAndUnzip(Vector<UInt64>): Load3xVectorAndUnzip failed:
 input: (15566609219474511423, 3770994876553725534, 110581834957594702, 3861262548139355537, 14869678267375981433, 8259632576148903608)
 result1: (0, 0)
 result2: (0, 0)
 result3: (0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_ulong() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load3xVectorAndUnzip.ulong.cs:line 62
   at Program.<<Main>$>g__TestExecutor2922|0_2923(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 73349
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
Test failed:
..........................................
..........................................
Sve.Load3xVectorAndUnzip(Vector<UInt64>): Load3xVectorAndUnzip failed:
 input: (17264867983810848622, 13917446457620629372, 11517230635455662426, 10995618029396180244, 1028553107680121528, 15564391984077529391)
 result1: (0, 0)
 result2: (0, 0)
 result3: (0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_ulong() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load3xVectorAndUnzip.ulong.cs:line 62
   at Program.<<Main>$>g__TestExecutor2922|0_2923(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 73349
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
Test failed:
..........................................
..........................................
Sve.Load3xVectorAndUnzip(Vector<UInt64>): Load3xVectorAndUnzip failed:
 input: (10680677860606493079, 17156796507167890225, 14559845466388441748, 9407654333740400678, 4647184485861503755, 5219064857065780344)
 result1: (0, 0)
 result2: (0, 0)
 result3: (0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_ulong() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load3xVectorAndUnzip.ulong.cs:line 62
   at Program.<<Main>$>g__TestExecutor2922|0_2923(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 73349
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
Test failed:
..........................................
..........................................
Sve.Load3xVectorAndUnzip(Vector<UInt64>): Load3xVectorAndUnzip failed:
 input: (13116702447767830730, 6418524644097684397, 18295063265548963677, 14505754193233054664, 13451472532994282358, 288081350472127268)
 result1: (0, 0)
 result2: (0, 0)
 result3: (0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_ulong() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load3xVectorAndUnzip.ulong.cs:line 62
   at Program.<<Main>$>g__TestExecutor2922|0_2923(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 73349
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
Test failed:
..........................................
..........................................
Sve.Load3xVectorAndUnzip(Vector<UInt64>): Load3xVectorAndUnzip failed:
 input: (8230511569220708254, 1499115774367769984, 17072457163727021516, 14901572143793325368, 14799134988725212856, 14804270624485750055)
 result1: (0, 0)
 result2: (0, 0)
 result3: (0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_ulong() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load3xVectorAndUnzip.ulong.cs:line 62
   at Program.<<Main>$>g__TestExecutor2922|0_2923(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 73349
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
Test failed:
..........................................
..........................................
Sve.Load3xVectorAndUnzip(Vector<UInt64>): Load3xVectorAndUnzip failed:
 input: (5410857252623066211, 16075851411137972360, 17514793739205811201, 5318905937370629901, 11487775543060089787, 7403572652654839548)
 result1: (0, 0)
 result2: (0, 0)
 result3: (0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_ulong() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load3xVectorAndUnzip.ulong.cs:line 62
   at Program.<<Main>$>g__TestExecutor2922|0_2923(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 73349
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
Test failed:
..........................................
..........................................
Sve.Load3xVectorAndUnzip(Vector<UInt64>): Load3xVectorAndUnzip failed:
 input: (10534931364653361766, 5757517814562190251, 6948549069997549466, 15288495555139533341, 9347443577998148460, 9173111324941758998)
 result1: (0, 0)
 result2: (0, 0)
 result3: (0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_ulong() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load3xVectorAndUnzip.ulong.cs:line 62
   at Program.<<Main>$>g__TestExecutor2922|0_2923(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 73349
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------
Test failed:
..........................................
..........................................
Sve.Load3xVectorAndUnzip(Vector<UInt64>): Load3xVectorAndUnzip failed:
 input: (10090648655723544362, 9760948327254045527, 10009983076607457179, 52253803498595597, 4604910486130183954, 11195811813855702886)
 result1: (0, 0)
 result2: (0, 0)
 result3: (0, 0)
..........................................
System.Exception: One or more scenarios did not complete as expected.
   at JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_ulong() in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\Arm\Sve\Sve_ro\Sve_ro\gen\Sve.Load3xVectorAndUnzip.ulong.cs:line 62
   at Program.<<Main>$>g__TestExecutor2922|0_2923(StreamWriter tempLogSw, StreamWriter statsCsvSw, <>c__DisplayClass0_0&) in c:\work\runtime\artifacts\tests\coreclr\obj\windows.arm64.Checked\Managed\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\generated\XUnitWrapperGenerator\XUnitWrapperGenerator.XUnitWrapperGenerator\FullRunner.g.cs:line 73349

C:\Users\Administrator\Desktop\wills>py .\stress_tester.py %CORE_ROOT%/corerun.exe "C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\HardwareIntrinsics_Arm_ro.dll" Sve_Load4xVector
Starting test: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root/corerun.exe C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_ro\HardwareIntrinsics_Arm_ro.dll Sve_Load4xVector
===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_float() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_double() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_sbyte() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_short() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_int() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_long() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_byte() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_ushort() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_uint() : 15
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_ulong() : 15
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
Errors:

Assert failure(PID 7436 [0x00001d0c], Thread: 17084 [0x42bc]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 398; hash 0x119699a2; Tier0-MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
Errors:

Assert failure(PID 9036 [0x0000234c], Thread: 7784 [0x1e68]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 398; hash 0x119699a2; Tier0-MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
Errors:

Assert failure(PID 18304 [0x00004780], Thread: 18692 [0x4904]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 398; hash 0x119699a2; Tier0-MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

C:\Users\Administrator\Desktop\wills>py .\stress_tester.py %CORE_ROOT%/corerun.exe "C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_r\HardwareIntrinsics_Arm_r.dll" Sve_Load2xVector
Starting test: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root/corerun.exe C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_r\HardwareIntrinsics_Arm_r.dll Sve_Load2xVector
===================Running default===================
------------------- {} -------------------
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_float() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_double() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_sbyte() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_short() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_int() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_long() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_byte() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_ushort() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_uint() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load2xVectorAndUnzip_ulong() : 15
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

C:\Users\Administrator\Desktop\wills>py .\stress_tester.py %CORE_ROOT%/corerun.exe "C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_r\HardwareIntrinsics_Arm_r.dll" Sve_Load3xVector
Starting test: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root/corerun.exe C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_r\HardwareIntrinsics_Arm_r.dll Sve_Load3xVector
===================Running default===================
------------------- {} -------------------
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_float() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_double() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_sbyte() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_short() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_int() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_long() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_byte() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_ushort() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_uint() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load3xVectorAndUnzip_ulong() : 15
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
Errors:

Assert failure(PID 1552 [0x00000610], Thread: 18340 [0x47a4]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load3xVectorAndUnzip_uintTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 330; hash 0x971a4f36; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
Errors:

Assert failure(PID 19172 [0x00004ae4], Thread: 18344 [0x47a8]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load3xVectorAndUnzip_uintTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 330; hash 0x971a4f36; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

C:\Users\Administrator\Desktop\wills>py .\stress_tester.py %CORE_ROOT%/corerun.exe "C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_r\HardwareIntrinsics_Arm_r.dll" Sve_Load4xVector
Starting test: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root/corerun.exe C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\JIT\HardwareIntrinsics\HardwareIntrinsics_Arm_r\HardwareIntrinsics_Arm_r.dll Sve_Load4xVector
===================Running default===================
------------------- {} -------------------
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_float() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_double() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_sbyte() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_short() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_int() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_long() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_byte() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_ushort() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_uint() : 15
Passed test: _Sve_r::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Load4xVectorAndUnzip_ulong() : 15
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
Errors:

Assert failure(PID 18240 [0x00004740], Thread: 17428 [0x4414]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 410; hash 0x119699a2; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2'} -------------------
Errors:

Assert failure(PID 19156 [0x00004ad4], Thread: 3492 [0x0da4]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 410; hash 0x119699a2; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
Errors:

Assert failure(PID 7732 [0x00001e34], Thread: 17780 [0x4574]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 410; hash 0x119699a2; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
Errors:

Assert failure(PID 13904 [0x00003650], Thread: 12732 [0x31bc]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 410; hash 0x119699a2; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
Errors:

Assert failure(PID 14264 [0x000037b8], Thread: 19136 [0x4ac0]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 410; hash 0x119699a2; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
Errors:

Assert failure(PID 16912 [0x00004210], Thread: 3640 [0x0e38]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 410; hash 0x119699a2; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
Errors:

Assert failure(PID 17180 [0x0000431c], Thread: 4448 [0x1160]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 410; hash 0x119699a2; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
Errors:

Assert failure(PID 7784 [0x00001e68], Thread: 17668 [0x4504]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 410; hash 0x119699a2; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
Errors:

Assert failure(PID 10796 [0x00002a2c], Thread: 8524 [0x214c]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 410; hash 0x119699a2; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
Errors:

Assert failure(PID 19204 [0x00004b04], Thread: 18808 [0x4978]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 410; hash 0x119699a2; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
Errors:

Assert failure(PID 6748 [0x00001a5c], Thread: 4248 [0x1098]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 410; hash 0x119699a2; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
Errors:

Assert failure(PID 18964 [0x00004a14], Thread: 18984 [0x4a28]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 410; hash 0x119699a2; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe


------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------
Errors:

Assert failure(PID 18136 [0x000046d8], Thread: 14080 [0x3700]): Assertion failed 'isValidSimm<9>(emitGetInsSC(id))' in 'JIT.HardwareIntrinsics.Arm._Sve.Sve_Load4xVectorAndUnzip_doubleTest:RunStructLclFldScenario_NonFaulting():this' during 'Generate code' (IL size 410; hash 0x119699a2; MinOpts)

    File: C:\work\runtime\src\coreclr\jit\emitarm64sve.cpp:14192
    Image: C:\Users\Administrator\Desktop\wills\windows.arm64.Checked\Tests\Core_Root\corerun.exe

Where the assertion appears:

        case IF_SVE_ID_2A: // ..........iiiiii ...iiinnnnn.TTTT -- SVE load predicate register
        case IF_SVE_JG_2A: // ..........iiiiii ...iiinnnnn.TTTT -- SVE store predicate register
            assert(insOptsNone(id->idInsOpt()));
            assert(isScalableVectorSize(id->idOpSize()));
            assert(isPredicateRegister(id->idReg1()));   // TTTT
            assert(isGeneralRegisterOrZR(id->idReg2())); // nnnnn
            assert(isValidSimm<9>(emitGetInsSC(id)));    // iii <------ ASSERTION FAILS
            break;

kunalspathak
kunalspathak requested changes May 26, 2024
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src/tests/JIT/HardwareIntrinsics/Arm/Shared/SveLoad2xVectorAndUnzipTest.template Outdated Show resolved Hide resolved
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TIHan commented May 28, 2024

@kunalspathak this is ready again.

kunalspathak
kunalspathak approved these changes May 28, 2024
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LGTM. Thanks!

@TIHan TIHan merged commit 21aa3b7 into dotnet:main May 29, 2024
161 of 167 checks passed
Ruihan-Yin pushed a commit to Ruihan-Yin/runtime that referenced this pull request May 30, 2024
@TIHan @Ruihan-Yin
SVE: Added Load2xVectorAndUnzip, Load3xVectorAndUnzip, `Load4xVec…
b1369f1 
…torAndUnzip` APIs (dotnet#102180)
@kunalspathak kunalspathak mentioned this pull request May 31, 2024
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@kunalspathak kunalspathak kunalspathak approved these changes

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area-System.Runtime.Intrinsics arm-sve Work related to arm64 SVE/SVE2 support new-api-needs-documentation
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@TIHan @kunalspathak @a74nh @tannergooding