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Support a few "shifted register" operations on Arm64 #75823
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch Issue DetailsThis makes progress towards #68028
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This has more substantial diffs: coreclr_tests.run.Linux.arm64.checked.mch
libraries.crossgen2.Linux.arm64.checked.mch:
libraries.pmi.Linux.arm64.checked.mch:
libraries_tests.pmi.Linux.arm64.checked.mch:
Similar numbers exist for other platforms. |
Example diffs are things like: - lsl w1, w1, #8
- orr w0, w0, w1
+ orr w0, w0, w1, LSL #8 The couple regressions that do show up are additional alignment bytes inserted, so not really regressions. |
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Rebase onto main to pick up #76061 |
…ster instructions
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/azp run runtime-coreclr jitstress, runtime-coreclr gcstress0x3-gcstress0xc, Fuzzlyn |
Azure Pipelines successfully started running 3 pipeline(s). |
/azp run runtime-coreclr jitstress, runtime-coreclr gcstress0x3-gcstress0xc, Fuzzlyn |
Azure Pipelines successfully started running 3 pipeline(s). |
gcstress failures are unrelated jitstress failures are related to the new |
This should be ready for review, CC. @dotnet/jit-contrib |
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Applied the formatting patch/squashed the applied fixes |
Co-authored-by: SingleAccretion <62474226+SingleAccretion@users.noreply.github.com>
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LGTM, nice diffs! and thanks @SingleAccretion for code review 🙂
This makes progress towards #68028