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[JIT] X64 - Centralize peephole optimization for removing redundant mov instructions #85780

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merged 10 commits into from May 11, 2023

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@TIHan TIHan commented May 4, 2023

Description

This centralizes checking for redundant mov instructions.

Depending on what we do for #85734 , we need to counter some of the regressions that may occur as a result of not removing CAST nodes.

This also includes more peephole optimizations for movzx, movsx and movsxd.

@dotnet-issue-labeler dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label May 4, 2023
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Issue Details

Description

Depending on what we do for #85734 , we need to counter some of the regressions that may occur as a result of not removing CAST nodes. For x64, we can do this by looking for redundant movzx and movsx instructions.

Author: TIHan
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area-CodeGen-coreclr

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@TIHan TIHan changed the title Added AreUpperBitsZero and AreUpperBitsSignExtended [JIT] X64 - Peephole optimization for removing redundant movzx and movsx instructions May 4, 2023
@TIHan TIHan changed the title [JIT] X64 - Peephole optimization for removing redundant movzx and movsx instructions [JIT] X64 - Centralization peephole optimization for removing redundant mov instructions May 4, 2023
@TIHan TIHan changed the title [JIT] X64 - Centralization peephole optimization for removing redundant mov instructions [JIT] X64 - Centralize peephole optimization for removing redundant mov instructions May 4, 2023
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TIHan commented May 5, 2023

/azp run runtime-coreclr gcstress0x3-gcstress0xc

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TIHan commented May 5, 2023

/azp run Fuzzlyn

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@TIHan TIHan marked this pull request as ready for review May 5, 2023 01:12
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TIHan commented May 5, 2023

/azp run Fuzzlyn

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TIHan commented May 5, 2023

@dotnet/jit-contrib this is ready. PTAL @BruceForstall - Diffs

All diff improvements, and we get a TP win for x64.
There is a significant TP regression for x86 which is likely because we never actually did any of these optimizations for x86 - we are now eliminating redundant movsx and movzx instructions.

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TIHan commented May 5, 2023

Thinking about it, I'm not sure why there are TP regressions for x86 for MinOpts. These optimizations only kick in when optimizations are on.

src/coreclr/jit/emitxarch.cpp Show resolved Hide resolved
src/coreclr/jit/emitxarch.cpp Show resolved Hide resolved
{
result = (id->idOpSize() <= size);
}
#ifdef TARGET_64BIT
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On 32-bit will EA_4BYTE ever be passed? If not, we don't technically don't need the ifdef?

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size can be EA_4BYTE on 32-bit - ifdef'ing this only for 64-bit just does less work on 32-bit.

result = (id->idOpSize() <= size);
}
#ifdef TARGET_64BIT
// movsx/movsxd always sign extends to 8 bytes. W-bit is set.
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Why does the W-bit matter here?

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@TIHan TIHan May 6, 2023

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W-bit on the encoding is what makes movsx and movsxd sign-extend to 8 bytes. We always default to using the W-bit. Technically, we could have a movsx or movsxd instruction not set the W-bit which would not sign-extend to 8 bytes (that would be a problem and make this optimization not safe), but we never actually emit those instructions that way.

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This function cares about instructions and sizes, but not encoding, though.

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The comment W-bit is set itself is just meant to inform the reason why this optimization is safe to do. It was already there before.

@ghost ghost added needs-author-action An issue or pull request that requires more info or actions from the author. and removed needs-author-action An issue or pull request that requires more info or actions from the author. labels May 6, 2023
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TIHan commented May 8, 2023

@BruceForstall This is ready again.

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TIHan commented May 10, 2023

@BruceForstall This is ready again. The optimizations only happen for X64, which was the case before, so no TP regressions for X86.

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Diffs

@TIHan TIHan merged commit e87dafa into dotnet:main May 11, 2023
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